Prosecution Insights
Last updated: April 19, 2026
Application No. 18/539,797

ELECTRONIC APPARATUS

Non-Final OA §103
Filed
Dec 14, 2023
Examiner
TOBERGTE, NICHOLAS J
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Shinko Electric Industries Co. Ltd.
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
1y 11m
To Grant
96%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allow Rate
837 granted / 886 resolved
+26.5% vs TC avg
Minimal +2% lift
Without
With
+2.0%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
28 currently pending
Career history
914
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
38.3%
-1.7% vs TC avg
§102
30.1%
-9.9% vs TC avg
§112
11.9%
-28.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 886 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gowda et al US 2017/0207160 and further in view of Rokugawa et al US 2003/0138992. Pertaining to claim 1, Gowda teaches electronic apparatus comprising: a lead frame 104 that is made of metal; a wiring board 88/42/64 that mounts an electronic component 68/70 bonded to the lead frame 104; and sealing resin that seals the lead frame, the electronic component, and the wiring board [0044] (polymer that fills cavity 108), wherein the lead frame 104 includes a first surface that is bonded to the electronic component and that is covered by the sealing resin, and a second surface that is located opposite to the first surface and that is exposed from the sealing resin See Figure 20 marked up below, the wiring board includes an insulating base material 42, a wiring layer 88 that is formed on a first surface of the insulating base material, and an adhesive layer 64 that is laminated on a second surface of the insulating base material on an opposite side of the first surface and that includes a second surface to which the electronic component is bonded See Figure 20 marked up below, and PNG media_image1.png 326 600 media_image1.png Greyscale Gowda fails to teach wherein the first surface of the insulating base material and the second surface of the adhesive layer are covered by the sealing resin. Rokugawa teaches a device 10 with a leadframe 20 encapsulated inside a sealing resin 36 that completely covers all of the layers and elements of the device 10. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the teaching of Rokugawa with the device of Gowda by completely encapsulating the device of Gowda leaving only portions of the leadframe exposed. The ordinary artisan would have been motivated to combine for the purposes of encapsulating and protecting the entire device from environmental damage. Note: “covers” is broad language and does not explicitly mean in contact or otherwise touching any particular layer or side. Pertaining to claim 2, Gowda in view of Rokugawa teaches the electronic apparatus according to claim 1, wherein the lead frame includes a heat sink that has the first surface that is bonded to the electronic component, and a lead that that is connected to a side surface located adjacent to the first surface and the second surface of the heat sink and that protrudes from the sealing resin. Based on the applicants drawings it appears that the “heat sink” and the “lead frame” are the same structure 120. As such it is not unreasonable to interpret the leadframe of Gowda as acting as a heat sink (metal conducts heat), additionally, Gowda teaches that the leadframe may have a heat sink (not shown) connected to it to further facilitate heat removal [0053]. Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gowda et al US 2017/0207160 and further in view of Rokugawa et al US 2003/0138992 and further in view of Li et al US 2004/0217450. Pertaining to claim 3, Gowda in view of Rokugawa teaches the electronic apparatus according to claim 1, but is silent wherein the first surface of the lead frame includes a recessed portion at a position corresponding to the electronic component, and the electronic component is housed in the recessed portion and bonded to a bottom surface of the recessed portion. Li teaches a recessed portion 313 in a leadframe 310 for housing an electronic component 320. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the teachings of Li into the device of Gowda by including a recessed portion in the leadframe for the electronic component. The ordinary artisan would have been motivated to modify Gowda in the manner set forth above for at least the purpose of securing the encapsulation body more firmly in position without delamination. See Abstract of Li. 4. The electronic apparatus according to claim 3, wherein the wiring board mounts a plurality of the electronic components with different thicknesses, the first surface of the lead frame includes a plurality of the recessed portions at positions corresponding to the plurality of the electronic components respectively, and the plurality of the recessed portions have bottom surfaces located at different depths from the first surface in accordance with the thicknesses of the plurality of the electronic components respectively. 5. The electronic apparatus according to claim 4, wherein the lead frame includes a plurality of regions that are separated from each other, and the plurality of the recessed portions are formed in the plurality of regions in a distributed manner and house the corresponding electronic components respectively. 6. The electronic apparatus according to claim 1, wherein the first surface of the lead frame includes a guide pin that stands from a position that does not overlap with the electronic component in plan view, and the wiring board includes an insertion hole in which the guide pin is inserted. 7. The electronic apparatus according to claim 1, wherein a first surface of the wiring layer opposite to the insulating base material is exposed from the sealing resin. Allowable Subject Matter Claims 4-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Pertaining to claim 4, the prior art does not teach nor suggest wherein the wiring board mounts a plurality of the electronic components with different thicknesses, the first surface of the lead frame includes a plurality of the recessed portions at positions corresponding to the plurality of the electronic components respectively, and the plurality of the recessed portions have bottom surfaces located at different depths from the first surface in accordance with the thicknesses of the plurality of the electronic components respectively. Pertaining to claim 6, the prior art does not teach nor suggest wherein the first surface of the lead frame includes a guide pin that stands from a position that does not overlap with the electronic component in plan view, and the wiring board includes an insertion hole in which the guide pin is inserted Pertaining to claim 7, the prior art does not teach nor suggest wherein a first surface of the wiring layer opposite to the insulating base material is exposed from the sealing resin. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Dec 14, 2023
Application Filed
Mar 16, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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SEMICONDUCTOR PACKAGES AND METHOD OF MANUFACTURING THE SAME
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
96%
With Interview (+2.0%)
1y 11m
Median Time to Grant
Low
PTA Risk
Based on 886 resolved cases by this examiner. Grant probability derived from career allow rate.

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