Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed February 13, 2026.
Status of claims to be treated in this office action:
a. Independent: 1, 19, 20
b. Pending: 1-20
Claims 1, 8, 19, and 20 have been amended.
Specification
The amendments to the Specification from the Office Action mailed November 13, 2025 have been reviewed and are accepted by the Examiner. Those objections to the Specification are withdrawn.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: Nonvolatile memory device and method of controlling the same to address disturbance between sub blocks.
Response to Arguments
Applicant’s arguments with respect to claims 1-14 and 16-20 have been considered but are moot because the new ground of rejection relies on a new combination of previously used references applied in the prior rejection of record. New grounds of rejection are made in view of Lutze et al. (US Pub. 20100002513 A1; “Lutze”) in view of Goda et al. (US Pub. 20240168878 A1; “Goda”). Goda paras. [0043]-[0045], and Figs. 1 and 5 are relevant to claims 1, 19, and 20.
During the interview on December 29, 2025, all parties agreed that the amendment to the first limitation of claim 1 overcame the rejection using Lutze (US Pub. 20100002513 A1). However, upon further search and consideration, several references including Goda (US Pub. 20240168878 A1), which was used in the previous office action, teach the first limitation of claim 1 and in combination with Lutze, together reject claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 6, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lutze (US Pub. 20100002513 A1) in view of Goda (US Pub. 20240168878 A1).
Regarding independent claim 1, Lutze discloses a method of controlling ([0080]: FIG. 7 is a flow chart describing a process for operating non-volatile storage) a nonvolatile memory device (Fig. 3: memory device 210), comprising:
performing a normal erase operation (Fig. 7: step 552; [0081]: In step 552, memory cells are erased (in blocks or other units) prior to programming) independently with respect to each sub block of the plurality of sub blocks of the memory block ([0059]: In one embodiment, the block is the unit of conventional erase. Other units of erase can also be used). Examiner asserts due to para. [0081] that a smaller unit may be used as the erase unit);
performing a disturbance verification read operation (Fig. 9: step 652; [0094]: In step 652, an erase verify operation is performed on the memory cells connected to the selected word line. The erase verify operation determines whether the memory cells have been properly erased) with respect to the first sub block to determine whether a threshold voltage of memory cells connected to a wordline in an erased state of the first sub block is increased higher than a reference level ([0094]: the erase verify operation determines whether the threshold voltages of the memory cells are greater then the erase verify compare voltage Vev (see FIG. 6A). The selected word line receives the erase verify compare voltage Vev and the unselected word lines receive an overdrive voltage (approximately 8 to 10 volts), sometimes referred to as Vread. As explained above with respect to step 612 of FIG. 8, after applying the appropriate word line voltages (which provides the voltages to the control gates), the conduction currents of the selected memory cells are observed/measured to determiner whether the memory cells are conducting. Memory cells that conduct in response to the erase verify voltage Vev are assumed to have a threshold voltage within state S0 and therefore are properly erased. Memory cells that do not conduct in response to receiving the erase verify voltage Vev and that are supposed to be in the erase state S0 are concluded to have threshold voltages that appear to be outside (e.g., above) the threshold voltage distribution for erase data state S0) by a program operation and a read operation with respect to the second sub block ([0078]: Memory cells can suffer from capacitive coupling from neighbor memory cells on the same word line, on the same bit line, or an adjacent word line and an adjacent bit line. The capacitive coupling serves to raise the apparent threshold voltage of a memory cell because the neighbor memory cell has been programmed; [0011]: the charge level read from the first memory cell appears to be different than programmed because of the effect of the charge on the adjacent memory cells being coupled to the first memory cell. The coupling from adjacent memory cells can shift the apparent charge level being read a sufficient amount to lead to an erroneous reading of the data stored; [0078]: a page or sector comprised of memory cells whose threshold voltages are overlapping cannot be correctly read back because the system will be unable to determine whether the cells are in state 0 or state 1; [0072] references a publication that includes compensation for coupling during read operations); and
selectively performing a post erase operation (Fig. 7: step 558 or Fig. 9: step 656; [0082]: In step 558, the memory system (at the direction of the controller and/or the state machine) selectively performs erase operations for (e.g. to re-erase) those memory cells that should be erased state but have threshold voltages that appear to be outside the threshold voltage distribution of the erased data state) with respect to the first sub block (Examiner asserts that it is clear from paras. [0081]-[0082] that erase operations may be performed on units smaller than a block) based on a result of the disturbance verification read operation ([0094]: the process continues at step 656 and a selective erase operation is performed on those memory cells that are supposed to be in a erase state S0 but that did not pass the verification process of step 652) to decrease the threshold voltage of memory cells ([0094]) in the erased state of the first sub block ([0082]).
Lutze does not disclose:
dividing a memory block of a plurality of memory blocks of the nonvolatile memory device into a plurality of sub blocks including a first sub block and a second sub block that are disposed in a vertical direction, wherein the memory block includes a plurality of cell strings, and each cell string includes a plurality of memory cells that are disposed in the vertical direction;
However, Goda teaches:
dividing a memory block (Fig. 5: memory array 502-0) of a plurality of memory blocks (memory arrays 502-0, 502-1, 502-3, and 502-4; [0043]) of the nonvolatile memory device (Fig. 1: memory device 100; [0043]) into a plurality of sub blocks ([0043]: deck) including a first sub block ([0044]: Each super deck (or super erase block) 515 can comprise a deck from each plane across multiple LUNs. For example, a first super deck 515-1 (SUPER DECK 1) can comprise a deck from plane 0 of LUN0. Examiner asserts that the topmost deck from plane 0 of LUN0 is analogous to a first sub block) and a second sub block (the second deck from the top of plane 0 of LUN0) that are disposed in a vertical direction (the two indicated decks are stacked vertically), wherein the memory block includes a plurality of cell strings, and each cell string includes a plurality of memory cells that are disposed in the vertical direction ([0045]: consider an example in which the constituent decks of a super deck 515-1 share common strings with the respective constituent decks of a super deck 515-2 (e.g., super decks 515-1 and 515-2 are located in a same physical super block); [0027]: The memory cells 223 of the strings 225 are stacked vertically);
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Goda to Lutze wherein the method comprises dividing a memory block of a plurality of memory blocks of the nonvolatile memory device into a plurality of sub blocks including a first sub block and a second sub block that are disposed in a vertical direction, wherein the memory block includes a plurality of cell strings, and each cell string includes a plurality of memory cells that are disposed in the vertical direction in order to mitigate bit error rates and data loss by providing methods to manage program disturb and erase disturb among blocks coupled to a common string (Goda, [0016]-[0017]).
Regarding claim 2, Lutze and Goda together disclose the limitations of claim 1. Lutze does not disclose:
wherein the first sub block and the second sub block share a same channel.
However, Goda teaches:
wherein the first sub block and the second sub block ( in reference to Fig. 3, [0034] teaches: In this example, the array 302 includes a plurality/group of word lines 322-1T, 322-2T, . . . , 322-NT corresponding to a first erase block 305-1 (e.g., a top deck) and a plurality/group of word lines 322-1B, 322-2B, . . . , 322-MB corresponding to a second erase block 305-2 (e.g., bottom deck)…embodiments can include more or fewer than four dummy word lines 331 separating erase blocks corresponding to same strings) share a same channel ([0035]: The array portion 302 illustrates two strings 325-1 and 325-2 for ease of illustration…the memory cells of a particular string 325 sharing a common channel region (e.g., pillar). Examiner concludes that each string traverses two memory blocks and so the blocks share same channels).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Goda to modified Lutze wherein the first sub block and the second sub block share a same channel in order to mitigate bit error rates and data loss by providing methods to manage program disturb and erase disturb among blocks coupled to a common string (Goda, [0016]-[0017]).
Regarding claim 6, Lutze and Goda together disclose the limitations of claim 1, and further through Lutze:
wherein the disturbance verification read operation with respect to the first sub block (Fig. 21: step 954; [0118]: Step 954 includes performing the process of FIG. 9) is performed before a program operation with respect to the first sub block is performed (step 956; [0118]: In step 956, the second pass of the two pass programming process will be performed on memory cells connected to WLn).
Independent claim 19 is nearly identical in claimed subject matter as claim 1
except for containing a control circuit and being drafted in device format instead of method format. All but the control circuit limitation are rejected for the same reasons as independent claim 1.
Lutze discloses a control circuit ([0058]: one or any combination of control circuitry 220, power control circuit 226, decoder circuit 224, state machine circuit 222, decoder circuit 242A, decoder circuit 242B, decoder circuit 240A, decoder circuit 240B, read/write circuits 230A, read/write circuits 230B, and/or controller 244 can be referred to as one or more managing or control circuits. The one or more managing or control circuits perform the processes described herein).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lutze (US Pub. 20100002513 A1) and Goda (US Pub. 20240168878 A1) as applied to claim 1 above, and further in view of Sun et al. (US Pat. 9343171 B1; “Sun”).
Regarding claim 3, Lutze and Goda together disclose the limitations of claim 1, and further through Lutze:
wherein performing the disturbance verification read operation (Fig. 9: step 652) includes:
applying a post erase verification voltage to the wordline in the erased state of the first sub block ([0094]: In step 652, an erase verify operation is performed on the memory cells connected to the selected word line…The selected word line receives the erase verify compare voltage Vev…After performing the selective erase process of step 656, the process loops back to step 652 and another erase verify process is performed) such that the post erase verification voltage (Vev) is higher than a normal erase verification voltage of the normal erase operation.
Neither Lutze nor Goda explicitly discloses:
applying a post erase verification voltage to the wordline in the erased state of the first sub block such that the post erase verification voltage is higher than a normal erase verification voltage of the normal erase operation.
However, Sun teaches:
applying a post erase verification voltage to the wordline in the erased state of the first sub block such that the post erase verification voltage is higher than a normal erase verification voltage of the normal erase operation (col. 14, lines 22-27: FIG. 7B depicts an example Vth distribution of data memory cells with four data states in an erase operation which uses a first erase-verify voltage VvEr1 for a first-programmed word line and the second erase-verify voltage VvEr2 for remaining word lines in the block. In this example, VvEr1<VvEr2).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Sun to modified Lutze wherein performing the disturbance verification read operation includes applying a post erase verification voltage to the wordline in the erased state of the first sub block such that the post erase verification voltage is higher than a normal erase verification voltage of the normal erase operation in order to provide a method which erases all word lines in a block to the same depth regardless of the number of word lines (Sun, col. 4, lines 19-24) and to optimize and adjust the erase-verify voltage level (col. 4, lines 43-47).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lutze (US Pub. 20100002513 A1) and Goda (US Pub. 20240168878 A1) as applied to claim 1 above, and further in view of Sun (US Pat. 9343171 B1) and Lee (US Pub. 20070121388 A1).
Regarding claim 4, Lutze and Goda together disclose the limitations of claim 1, and further through Lutze:
wherein selectively performing the post erase operation (Fig. 7: step 558) includes:
Neither Lutze nor Goda discloses:
applying a post erase voltage to channels of the first sub block such that the post erase voltage is lower than a normal erase voltage of the normal erase operation; and
applying a post erase verification voltage to the wordline in the erased state of the first sub block such that the post erase verification voltage is higher than a normal erase verification voltage of the normal erase operation.
However, Sun teaches:
applying a post erase verification voltage to the wordline in the erased state of the first sub block such that the post erase verification voltage is higher than a normal erase verification voltage of the normal erase operation (col. 14, lines 22-27).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Sun to modified Lutze wherein selectively performing the post erase operation includes: applying a post erase verification voltage to the wordline in the erased state of the first sub block such that the post erase verification voltage is higher than a normal erase verification voltage of the normal erase operation in order to provide a method which erases all word lines in a block to the same depth regardless of the number of word lines (Sun, col. 4, lines 19-24) and to optimize and adjust the erase-verify voltage level (col. 4, lines 43-47).
Neither Lutze, Goda, nor Sun discloses:
applying a post erase voltage to channels of the first sub block such that the post erase voltage is lower than a normal erase voltage of the normal erase operation; and
However, Lee discloses:
applying a post erase voltage to channels of the first sub block such that the post erase voltage is lower than a normal erase voltage of the normal erase operation ([0065]: Meanwhile, if data of a non-erase state (for example, 0), of data output from the Y-decoder (refer to numeral 180 in FIG. 4), are detected (i.e., the erase operation has failed) in the operation of determining whether the erase operation has been performed properly, the third pump circuit 63 may decrease the level of the erase voltage V.sub.ERS on a 0.1 to 0.5 V basis); and
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lee to modified Lutze wherein selectively performing the post erase operation includes: applying a post erase voltage to channels of the first sub block such that the post erase voltage is lower than a normal erase voltage of the normal erase operation in order to prevent leakage current in switching elements (Lee, [0099]), preserve data storage capacity ([0100]), and extend the lifespan of memory cells ([0101]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lutze (US Pub. 20100002513 A1), Goda (US Pub. 20240168878 A1), Sun (US Pat. 9343171 B1), and Lee (US Pub. 20070121388 A1) as applied to claim 4 above, and further in view of Jung et al. (US Pub. 20210335434 A1; “Jung”).
Regarding claim 5, Lutze, Goda, Sun, and Lee together disclose the limitations of claim 4. Further, through Lee:
wherein the post erase voltage of a first erase loop of the post erase operation is lower than the normal erase voltage of a first erase loop of the normal erase operation ([0065] teaches a post erase voltage that is lower than the normal erase voltage).
Neither Lutze, Goda, Sun, nor Lee discloses:
wherein the normal erase operation and the post erase operation are performed by an incremental step pulse erasing (ISPE) scheme, and
erase loops
However, Jung teaches:
wherein the normal erase operation and the post erase operation are performed by an incremental step pulse erasing (ISPE) scheme ([0084]: the selected memory block BLK may be erased based on an incremental step pulse erase (ISPE) manner...a magnitude of an erase voltage for an erase operation may stepwise increase. When the erase procedure reaches the predetermined number of erase loops without being determined as a pass, the erase procedure is determined as a fail. Examiner concludes that if one erase operation is performed by an ISPE scheme, other erase operations may also be performed by an ISPE scheme), and
erase loops ([0050]: the erase operation may include a plurality of erase loops)
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Jung to modified Lutze wherein the normal erase operation and the post erase operation are performed by an incremental step pulse erasing (ISPE) scheme, and there are erase loops in order to improve reliability of a nonvolatile memory device by detecting soft defects during erase delta verification (Jung, [0054]).
Claims 7, 8, 10, and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Lutze (US Pub. 20100002513 A1) and Goda (US Pub. 20240168878 A1) as applied to claim 6 above, and further in view of Lien et al. (US Pub. 20230069260 A1; “Lien”).
Regarding claim 7, Lutze and Goda together disclose the limitations of claim 6. Neither Lutze nor Goda discloses:
subsequent to determining that the result of the disturbance verification read operation indicates that the threshold voltage of the memory cells connected to the wordline in the erased state of the first sub block is increased higher than the reference level, determining whether an available free sub block in the erased state exists.
However, Lien teaches:
subsequent to determining that the result of the disturbance verification read operation indicates that the threshold voltage of the memory cells connected to the wordline in the erased state of the first sub block is increased higher than the reference level (Fig. 18A: step 1801; [0204]: Step 1801 includes determining a program or erase status of unselected sub-blocks of the block; [0226]: Erase disturb refers to an increase in the upper tail of the Vth distribution when memory cells in an unselected sub-block are inadvertently programmed in an erase operation for a selected sub-block in the same block. Examiner concludes that erase status may be affected by erase disturb), determining whether an available free sub block in the erased state exists (Fig. 18E: steps 1850 through 1853; [0216]: Step 1850 includes performing read operations to identify free blocks, sub-blocks and a word line program order; [0221]: With decision step 1853, the subsequent reading of the one or more interior SBs in step 1855 can be omitted if the source- and drain-side SBs are both programmed. If the source- and drain-side SBs are both programmed, step 1854 indicates there are no free SBs in the block. If the source- and drain-side SBs are not both programmed, step 1855 includes reading an interior SB at both edge WLs to determine if the SB is programmed. Examiner concludes that the result of step 1853 determines whether a free block is available).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lien to modified Lutze wherein subsequent to determining that the result of the disturbance verification read operation indicates that the threshold voltage of the memory cells connected to the wordline in the erased state of the first sub block is increased higher than the reference level, determining whether an available free sub block in the erased state exists in order to mitigate issues that arise from an increasing block size (Lien, [0054]).
Regarding claim 8, Lutze, Goda, and Lien together disclose the limitations of claim 7. Neither Lutze nor Goda discloses:
wherein, subsequent to determining that the available free sub block exists, the program operation with respect to the first sub block is replaced with the program operation with respect to the available free sub block and programming with respect to the first sub block is inhibited.
However, Lien teaches:
wherein, subsequent to determining that the available free sub block exists (Fig. 18E: steps 1850 through 1853), the program operation with respect to the first sub block is replaced with the program operation with respect to the available free sub block and programming with respect to the first sub block is inhibited (per Fig. 18A: step 1803 and Fig. 18E: step 1857, the program order is updated based on erase and program status and the presence of a free block).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lien to modified Lutze wherein subsequent to determining that the available free block exists, the program operation with respect to the first sub block is replaced with the program operation with respect to the available free sub block and programming with respect to the first sub block is inhibited in order to mitigate issues that arise from an increasing block size (Lien, [0054]).
Regarding claim 10, Lutze, Goda, and Lien together disclose the limitations of claim 7. Neither Lutze nor Goda discloses:
wherein, subsequent to determining that the available free sub block does not exist and all wordlines of the first sub block are in the erased state, the program operation with respect to the first sub block is performed after the post erase operation with respect to the first sub block is completed.
However, Lien teaches:
wherein, subsequent to determining that the available free sub block does not exist and all wordlines of the first sub block are in the erased state (Fig. 18E: step 1854; [0221]: If the source- and drain-side SBs are both programmed, step 1854 indicates there are no free SBs in the block), the program operation with respect to the first sub block is performed after the post erase operation with respect to the first sub block is completed ([0215]: A free block is a block with one or more free sub-blocks, e.g., blocks that are currently erased and which can be pre-charged for programming; also see Fig. 18A, steps 1802 and 1803. Examiner concludes that if there are no free blocks, the program operation of step 1803 may be performed after a block is successfully erased).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lien to modified Lutze wherein subsequent to determining that the available free sub block does not exist and all wordlines of the first sub block are in the erased state, the program operation with respect to the first sub block is performed after the post erase operation with respect to the first sub block is completed in order to mitigate issues that arise from an increasing block size (Lien, [0054]).
Regarding claim 12, Lutze and Goda together disclose the limitations of claim 6. Neither Lutze nor Goda discloses:
subsequent to determining that the result of the disturbance verification read operation indicates that the threshold voltage of the memory cells connected to the wordline in the erased state of the first sub block is not increased higher than the reference level, the post erase operation with respect to the first sub block is omitted and the program operation with respect to the first sub block is performed.
However, Lien teaches:
subsequent to determining that the result of the disturbance verification read operation indicates that the threshold voltage of the memory cells connected to the wordline in the erased state of the first sub block is not increased higher than the reference level (Fig. 18A: step 1801. Examiner notes that the erase status check determines whether the sub-block is fully erased), the post erase operation with respect to the first sub block is omitted and the program operation with respect to the first sub block is performed (Fig. 18A: step 1803).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lien to modified Lutze wherein subsequent to determining that the result of the disturbance verification read operation indicates that the threshold voltage of the memory cells connected to the wordline in the erased state of the first sub block is not increased higher than the reference level, the post erase operation with respect to the first sub block is omitted and the program operation with respect to the first sub block is performed in order to mitigate issues that arise from an increasing block size (Lien, [0054]).
Regarding claim 13, Lutze, Goda, and Lien together disclose the limitations of claim 12. Neither Lutze nor Goda discloses:
wherein the disturbance verification read operation and the post erase operation are performed while the nonvolatile memory device receives write data for the program operation from a host device.
However, Lien teaches:
wherein the disturbance verification read operation and the post erase operation are performed while the nonvolatile memory device receives write data for the program operation from a host device ([0108]: During program or verify operations for memory cells, the data to be programmed (write data) is stored in the set of data latches 194-197 from the data bus 120; [0063]: Commands and data are transferred between the host 140 and controller 122 via a data bus 120, and between the controller and the one or more memory die 108 via lines 118).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lien to modified Lutze wherein the disturbance verification read operation and the post erase operation are performed while the nonvolatile memory device receives write data for the program operation from a host device in order to mitigate issues that arise from an increasing block size (Lien, [0054]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lutze (US Pub. 20100002513 A1), Goda (US Pub. 20240168878 A1), and Lien (US Pub. 20230069260 A1) as applied to claim 8 above, and further in view of Um (US Pat. 9697903 B1) and Lee (US Pub. 20200082891 A1; “Lee-2”).
Regarding claim 9, Lutze, Goda and Lien together disclose the limitations of claim 8. Neither Lutze, Goda, nor Lien discloses:
wherein the post erase operation with respect to the first sub block is performed as a background operation, and
wherein, after the post erase operation with respect to the first sub block is completed, the first sub block is set as a free sub block such that programming with respect to the first sub block is permitted.
However, Um teaches:
wherein the post erase operation with respect to the first sub block is performed as a background operation (col. 10, lines 53-57: when the data storage device 300 operates in a background mode, the erase operation control module EC may provide a fine erase command so that memory cells of the nonvolatile memory device 100 are erased by a fine erase operation), and
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Um to modified Lutze wherein the post erase operation with respect to the first sub block is performed as a background operation in order to make memory cell threshold voltage distributions denser by erasing using a stepwise method (Um, col. 6, lines 38-41).
Also, through Lee-2:
wherein, after the post erase operation with respect to the first sub block is completed, the first sub block is set as a free sub block such that programming with respect to the first sub block is permitted ([0152]: The program control circuitry 1018 may perform a process of selecting a free block…the program control circuitry 1018 may select a free block having the lowest erase count among the at least selected free block. The program control circuitry 1018 may perform a process of programming or writing data to that free block selected based on its erase count value. Examiner concludes that erased blocks are set as free blocks and may be programmed thereafter).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lee-2 to modified Lutze wherein after the post erase operation with respect to the first sub block is completed, the first sub block is set as a free sub block such that programming with respect to the first sub block is permitted in order to measure the status of each memory block using erase count as an indicator of block health (Lee-2, [0006]-[0007]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lutze (US Pub. 20100002513 A1), Goda (US Pub. 20240168878 A1), and Lien (US Pub. 20230069260 A1) as applied to claim 7 above, and further in view of Lee-2 (US Pub. 20200082891 A1).
Regarding claim 11, Lutze, Goda, and Lien together disclose the limitations of claim 7. Lien discloses:
the program operation with respect to the first sub block is replaced with the program operation with respect to the available free sub block (Fig. 18A: step 1803 and Fig. 18E: step 1857).
Neither Lutze, Goda, nor Lien discloses:
wherein, subsequent to determining that the available free sub block does not exist and at least one wordline of the first sub block is in a programmed state, the available free sub block is generated by performing a garbage collection operation
However, Lee-2 teaches:
wherein, subsequent to determining that the available free sub block does not exist and at least one wordline of the first sub block is in a programmed state, the available free sub block is generated by performing a garbage collection operation ([0100]: the block manager 48 may select and erase blocks having no valid pages when a free block is needed. Furthermore, the block manager 48 may select a block including the least valid page when it is determined that garbage collection is necessary. The state manager 42 may perform garbage collection to move the valid data to an empty block and erase the blocks containing the moved valid data so that the block manager 48 may have enough free blocks (i.e., empty blocks with no data))
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lee-2 to modified Lutze wherein subsequent to determining that the available free sub block does not exist and at least one wordline of the first sub block is in a programmed state, the available free sub block is generated by performing a garbage collection operation in order to measure the status of each memory block using erase count as an indicator of block health (Lee-2, [0006]-[0007]).
Claims 14, 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lutze (US Pub. 20100002513 A1) and Goda (US Pub. 20240168878 A1) as applied to claim 1 above, and further in view of Uematsu et al. (US Pub. 20120215968 A1; “Uematsu”).
Regarding claim 14, Lutze and Goda together disclose the limitations of claim 1, and further through Lutze:
wherein the disturbance verification read operation with respect to the first sub block (Fig. 21: step 954)
Neither Lutze nor Goda explicitly discloses:
is performed before the normal erase operation with respect to the second sub block is performed.
However, Uematsu teaches:
wherein the disturbance verification read operation with respect to the first sub block is performed before the normal erase operation with respect to the second sub block is performed (per Fig. 3, step 160, which is analogous to a disturbance verification read operation with respect to the first sub block, may be performed before a normal erase occurs during step 150, as long as step 180 results in “yes”).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Uematsu to modified Lutze wherein the disturbance verification read operation with respect to the first sub block is performed before the normal erase operation with respect to the second sub block is performed in order to prevent an increase in data copy operations between blocks (Uematsu, [0006]).
Regarding claim 16, Lutze, Goda, and Uematsu together disclose the limitations of claim 14, and further through Lutze:
wherein, subsequent to determining that the result of the disturbance verification read operation indicates that the threshold voltage of the memory cells connected to the wordline in the erased state of the first sub block is increased higher than the reference level and at least one wordline of the first sub block is in a programmed state ([0094]),
Neither Lutze nor Goda discloses:
the post erase operation with respect to the first sub block is inhibited while the normal erase operation with respect to the second sub block is performed and programming with respect to the first sub block is inhibited.
However, Uematsu teaches:
the post erase operation with respect to the first sub block is inhibited while the normal erase operation with respect to the second sub block is performed and programming with respect to the first sub block is inhibited (per Fig. 3, one block is processed at a time, so if the second block is being programmed, the first block is not being programmed or post-erased).
Regarding claim 17, Lutze, Goda, and Uematsu together teach the method of claim 14, and further through Lutze:
wherein, subsequent to determining that the result of the disturbance verification read operation indicates that the threshold voltage of the memory cells connected to the wordline in the erased state of the first sub block is not increased higher than the reference level, the post erase operation with respect to the first sub block is inhibited and the normal erase operation with respect to the second sub block is performed (Lutze teaches in Fig. 9, once all the memory cells are erased, which is when the memory cells have a threshold voltage below the reference level, the operation will be considered complete and the memory cells will be inhibited from further erase operation).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lutze (US Pub. 20100002513 A1) and Goda (US Pub. 20240168878 A1) as applied to claim 1 above, and further in view of Yu et al. (US Pub. 20190198117 A1; “Yu”).
Regarding claim 18, Lutze and Goda together disclose the limitations of claim 1. Neither Lutze nor Goda discloses:
providing a plurality of intermediate switching transistors disposed in a boundary portion between two adjacent sub blocks in the vertical direction; and
selectively activating the plurality of intermediate switching transistors based on a position of a sub block where the normal erase operation or the post erase operation is performed.
However, Yu teaches:
providing a plurality of intermediate switching transistors disposed in a boundary portion between two adjacent sub blocks in the vertical direction; and
selectively activating the plurality of intermediate switching transistors based on a position of a sub block where the normal erase operation or the post erase operation is performed ([0007]: A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Yu to modified Lutze wherein the disturbance verification read operation with respect to the first sub block is performed before the normal erase operation with respect to the second sub block is performed in order to reduce disturbances and thus improve performance and lifetime of the device by activating switching transistors individually (Yu, [0010]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lutze (US Pub. 20100002513 A1) in view of Goda (US Pub. 20240168878 A1), and further in view of Song et al. (US Pub. 20200411122 A1; “Song”).
Independent claim 20 contains limitations that are substantially the same as independent claim 19, and those limitations are thus rejected for the same reasons using Lutze and Goda.
Neither Lutze nor Goda discloses:
a plurality of first bonding metal patterns disposed in a cell region;
a plurality of second bonding metal patterns disposed in a peripheral region disposed under the cell region, wherein the peripheral region is vertically coupled to the cell region by the plurality of first bonding metal patterns and the plurality of second bonding metal patterns;
However, Song teaches:
a plurality of first bonding metal patterns disposed in a cell region ([0197]: In the external pad bonding area PA, the memory device 2000 may include a lower metal pattern 2273a in an uppermost metal layer of the peripheral circuit region PERI. The lower metal pattern 2273a may correspond to an upper metal pattern 2372a formed in an uppermost metal layer of the cell region CELL);
a plurality of second bonding metal patterns disposed in a peripheral region disposed under the cell region, wherein the peripheral region is vertically coupled to the cell region by the plurality of first bonding metal patterns and the plurality of second bonding metal patterns ([0199]: Furthermore, the bitline bonding area BLBA, an upper metal pattern 2392, corresponding to a lower metal pattern 2252 formed in the uppermost metal layer of the peripheral circuit region PERI; also, per the abstract: The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad);
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Song to modified Lutze wherein a nonvolatile memory device comprises a plurality of first bonding metal patterns disposed in a cell region; and a plurality of second bonding metal patterns disposed in a peripheral region disposed under the cell region, wherein the peripheral region is vertically coupled to the cell region by the plurality of first bonding metal patterns and the plurality of second bonding metal patterns in order to improve the reliability of an erase operation (Song, [0004]).
Allowable Subject Matter
Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Li et al. (US Pub. 20250068327 A1): paras. [0084] and [0151], and Fig. 4a are relevant to claims 1, 19, and 20.
Song et al. (US Pub. 20190371410 A1): paras. [0065], [0126], and [0150], and Figs. 19 and 21 are relevant to claims 1, 19, and 20.
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/E.R.A./Examiner, Art Unit 2824
4/6/2026
/PHO M LUU/Primary Examiner, Art Unit 2824