DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of species I, corresponding to claims 1-10, 16-20 in the reply filed on May 11th, 2026 is acknowledged. The traversal is on the grounds that there is no serious search burden because the present application presents 20 total and 3 independent claims or that some example embodiments may include features from multiple figures. This is not found persuasive because the number of claims has minimal bearing on search burden. Furthermore, applicant does not specifically address the reasons for distinctness of the separated species or the reasons for search burden laid out in the previous requirement for restriction/election.
The requirement is still deemed proper and is therefore made FINAL.
Status of Claims
The status of the claims is as follows:
Claims 1-10, 16-20 are pending.
Claims 11-15 are withdrawn.
An action on the merits for claims 1-10, 16-20 follows.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
However, should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)- (d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
IDS
All references provided in the IDS have been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Memory Device Comprising Improved Backside Metal Layer Structure.
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10, 16, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20220352179 A1), hereinafter Yang in view of Do et al (US 20210384106 A1).
Regarding Claim 1, Yang teaches a semiconductor memory device ("vertical SRAM," (10); Figs. 2A-2D (show different cross-sections of one device), Paragraph [0018]) , comprising:
a substrate ("substrate," (100); Fig. 2C, Paragraph [0018]) that has a first surface ("frontside;" Fig. 2C, Paragraph [0021]) and a second surface ("backside," Fig. 2C, Paragraph [0015]) opposite to the first surface (frontside);
a lower active region (LAR; Annotated Fig. 2C) on the first surface (frontside), the lower active region (LAR) including a first lower gate electrode (lower section of "metal gate," (130B); Fig. 2C, Paragraph [0024]) and a first lower active contact (“source/drain contact,” (180B); Paragraph [0035]) spaced apart from the first lower gate electrode (lower section of 130B);
an upper active region (UAR; Annotated Fig. 2C) on the lower active region (LAR), the upper active region (UAR) including a first upper gate electrode (upper section of "metal gate," (130B); Fig. 2C, Paragraph [0024]) and a first upper active contact ("source/drain contact," (150A); Paragraph [0032]) spaced apart from the first upper gate electrode (upper section of 130B),
a first metal layer ("frontside routing structure," (148A); Paragraph [0031]) on the first surface (frontside); and
a backside metal layer ("backside routing structure," (148B); Paragraph [0031]) on the second surface (backside),
wherein the first upper gate electrode (upper section of 130B) and the first lower gate electrode (lower section of 130B) are connected and form a first gate electrode ("metal gate," (130B); Paragraph [0018]; part of "gate line," (20B); Fig. 2A), and
the first metal layer (148A) includes a first node line ("metal line," (170A); Fig. 2A, Paragraph [0033]) that electrically connects the first gate electrode (130B) to the first upper active contact (150A).
(Note: hereinafter, references refer to Yang unless otherwise specified)
Annotated Fig. 2C, Yang
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Yang does not explicitly teach the first upper active contact vertically overlapping at least part of the first lower active contact; and
a first connection structure that vertically connects the first upper active contact to the first lower active contact.
Do teaches at least a semiconductor device (“integrated circuit device;” Figs. 4, 5A-5C (cross sections of Fig. 4), Paragraph [0038]) comprising a first upper active contact (“upper routing contact,” (rightmost 27_U2); Fig. 5C, Paragraph [0054]) vertically overlapping at least part of the first lower active contact (“lower routing contact,” (rightmost 27_L2); Fig. 5C, Paragraph [0054]); and
a first connection structure (“output via,” (10_1); Paragraph [0054]) that vertically connects the first upper active contact (rightmost 27_U2) to the first lower active contact (rightmost 27_L2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Do into the device of Yang such that the device comprises a first connection structure that vertically connects vertically overlapping active contacts. This is because including such a structure allows for an upper and lower source/drain feature to be electrically connected, improving the electrical properties of the device and providing a common electrical path for the source/drain elements in each cell of the device Paragraph [0041, 0042]).
Regarding Claim 2, Yang as modified by Do teaches the device of claim 1, wherein
the lower active region (LAR) further includes a second lower gate electrode (lower section of "metal gate," (130A); Fig. 2C, Paragraph [0024]) and a second lower active contact (“source/drain contact,” (180A); Paragraph [0035]) spaced apart from the second lower gate electrode (lower section of 130A),
the upper active region (UAR) further includes a second upper gate electrode (upper section of "metal gate," (130A); Fig. 2C, Paragraph [0024]) and a second upper active contact ("source/drain contact," (150B); Paragraph [0032]) spaced apart from the second upper gate electrode (upper section of 130A),
the second upper gate electrode (upper section of 130A) and the second lower gate electrode (lower section of 130A) are connected and form a second gate electrode ("metal gate," (130A); Paragraph [0018]; part of "gate line," (20A); Fig. 2A), and
the first metal layer (148A) further includes a second node line ("metal line," (170B); Fig. 2A; Paragraph [0033]) that electrically connects the second gate electrode (130A) to the second upper active contact (150B).
Yang as modified by Do does not explicitly teach where the second upper active contact vertically overlaps at least part of the second lower active contact,
the second upper active contact and the second lower active contact are vertically connected through a second connection structure.
Do further teaches at least a semiconductor memory device “integrated circuit device;” Figs. 4, 5A-5C (cross sections of Fig. 4), Paragraph [0038]) wherein the second upper active contact “upper routing contact,” (leftmost 27_U2); Fig. 5C, Paragraph [0054]) vertically overlaps at least part of the second lower active contact (“lower routing contact,” (leftmost 27_L2); Fig. 5C, Paragraph [0054]),
the second upper active contact (leftmost 27_U2) and the second lower active contact (leftmost 27_L2) are vertically connected through a second connection structure (“output via,” (10_3); Paragraph [0054]).
Regarding Claim 3, Yang as modified by Do teaches the device of claim 2, wherein the first node line (170A) corresponds to an output end of a first inverter of a static random access memory (SRAM) cell, and the second node line (170B) corresponds to an output end of a second inverter of the SRAM cell ("Pass-gate transistor PG-1 is connected to an output of Inverter-1 a[…], and pass-gate transistor PG-2 is connected to an output of Inverter-2;" Figs. 1, 2A, Paragraph [0016] the pass gates are connected to respective metal lines 170A and 170B, therefore corresponding to output ends of respective inverters).
Regarding Claim 4, Yang as modified by Do teaches the device of claim 2, wherein the first node line (170A) and the second node lines (170B) have bar shapes which extend in parallel to each other (Fig. 2A).
Regarding Claim 5, Yang as modified by Do teaches the device of claim 1, wherein the lower active region (LAR) further includes a second lower active contact ("source/drain contact," (180A); Paragraph [0035]) between the first lower gate electrode (lower section of 130B) and the first lower active contact ("source/drain contact," (180B); Paragraph [0035]),
the upper active region (UAR) further includes a second upper active contact (source/drain contact," (150C); Paragraph [0032]) between the first upper gate electrode (upper section of 130B) and the first upper active contact ("source/drain contact," (150A); Paragraph [0032]),
the second upper active contact (150C) vertically overlaps at least part of the second lower active contact (180A),
the backside metal layer includes a ground line ("ground voltage, such as Vss," (185A); Paragraph [0035]) and
the ground line (185A) is electrically connected to the second lower active contact (180A).
Yang as modified by Do does not explicitly teach a semiconductor memory device wherein the backside metal layer includes a power line, and
The power line is electrically connected to the second upper contact.
Do further teaches at least a semiconductor memory device (“integrated circuit device;” Figs. 4, 5A-5C (cross sections of Fig. 4), Paragraph [0038]) wherein the backside metal layer (layer including power lines P1 and P2) includes a power line (“power line,” (P2); Fig. 5A, Paragraph [0024]), and
The power line (P2) is electrically connected to the second upper contact (“upper routing contact,” (27U_1); Fig. 5A, Paragraph [0031]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further incorporate the teachings of Do into the device of Yang such that the device includes a power line in its backside metal layer and the power line is electrically connected to the second upper active contact. This is because the power line can be placed to overlap a cell boundary, providing an electrical pathway for multiple source/drains, decreasing size and increasing efficiency Paragraphs [0055]).
Regarding Claim 6, Yang as modified by Do teaches the device of claim 5, wherein the second upper active contact (150C) includes a first portion that vertically overlaps at least part of the second lower active contact (180A) and at least part of a second portion other than the first portion (Fig. 2A shows the top of the semiconductor device including 150C and Fig. 2B shows the bottom of the semiconductor device including 180A. The upper contact clearly extends beyond the region marked '15' whereas the lower contact does not).
Yang as modified by Do does not explicitly teach
a first lower via that electrically connects the ground line to the second lower active contact; and
a second lower via that electrically connects the power line to the second upper active contact,
and the second lower via is coupled to the second portion.
Do further teaches a semiconductor memory device (“integrated circuit device;” Figs. 4, 5A-5C (cross sections of Fig. 4), Paragraph [0038]), comprising a first lower via (“first power via,” (20_13); Fig. 5A, Paragraph [0055]) that electrically connects the ground line (“first power line […] may be an electrical ground voltage,” (P1); Paragraphs [0024, 0047]) to the second lower active contact (“lower routing contact,” (27_L1); Paragraph [0049]); and
a second lower via (“second power via,” (30_3); Paragraph [0050]) that electrically connects the power line (“power line,” (P2); Fig. 5A, Paragraph [0024]) to the second upper active contact (“upper routing contact,” (27_U1); Paragraph [0050]),
wherein the second upper active contact (27_U1) includes a first portion that vertically overlaps at least part of the second lower active contact (27_L1) and at least part of a second portion other than the first portion, and the second lower via (30_3) is coupled to the second portion (In Do Fig. 5A, it is seen that the second lower via 30_3 extends along the side of the lower active contact 27_L1 in order to contact the upper active contact 27_U1 on a region not overlapping the lower active contact 27_L1, otherwise the via would also contact the lower active contact).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further incorporate the teachings of Do into the device of Yang such that the device includes a first lower via electrically connecting the ground line to the second lower active contact and a second lower via electrically connecting the power line to the second upper active contact. This is because arranging the lower vias in this manner allows for the power and ground lines to be located on cell boundaries, with vias providing electrical pathways for multiple cells along those boundaries while decreasing the total amount of space needed and increasing efficiency (Paragraphs [0055, 0003]).
Regarding Claim 7, Yang as modified by Do teaches the device of claim 5, wherein the backside metal layer (148B) further includes a bit line ("bit line," (185B); Fig. 2C, Paragraph [0035]).
Regarding Claim 8, Yang as modified by Do teaches the device of claim 1, wherein the first metal layer (148A) further includes a word line ("word line," (170D); Fig. 2C, Paragraph [0033]).
Regarding Claim 10, Yang as modified by Do teaches the device of claim 1, wherein the lower active region (LAR) includes a first pull-down transistor ("pull-down transistor," (PD-1 / M1); Fig. 2C, Paragraph [0028]) and a second pull-down transistor ("pull-down transistor," (PD-2 / M3); Paragraph [0028]),
the upper active region (UAR) includes a first pull-up transistor ("pull-up transistor," (PU-1 / M2); Paragraph [0028] and a second pull-up transistor ("pull-up transistor," (PU-2 / M4); Paragraph [0028]),
the first lower active contact (180B) is connected to a source/drain ("source/drain feature," (120B); Paragraph [0022]) of the first pull-down transistor (PD-1 / M1),
the first upper active contact (150A) is connected to a source/drain ("source/drain feature," (120A); Paragraph [0022]) of the first pull-up transistor (PU-1 / M2),
the first lower gate electrode (lower section of 130B) is connected to a gate (130B, Paragraph [0030]) of the second pull- down transistor (PD-2 / M3), and
the first upper gate electrode (upper section of 130B) is connected to a gate (130B, Paragraph [0030]) of the second pull-up transistor (PU-2 / M4).
Regarding Claim 16, Yang teaches a semiconductor memory device ("vertical SRAM," (10); Figs. 2A-2D, Paragraph [0018]), comprising:
a substrate ("substrate," (100); Fig. 2C, Paragraph [0018]) including a first surface ("frontside;" Fig. 2C, Paragraph [0021]) and a second surface ("backside," Fig. 2C, Paragraph [0015]) opposite to the first surface (frontside);
a lower active region (LAR; Annotated Fig. 2C) on the first surface (frontside), the lower active region (LAR) including a lower channel pattern ("semiconductor layer," (110D); Paragraph [0021]) and a lower source/drain pattern ("source/drain feature," (120B); Paragraph [0020]);
an upper active region (UAR; Annotated Fig. 2C) on the lower active region (LAR), the upper active region (UAR) including an upper channel pattern ("semiconductor layer," (110C); Paragraph [0021]) and an upper source/drain pattern ("source/drain feature," (120A); Paragraph [0020]);
a lower gate electrode (lower section of "metal gate," (130B); Fig. 2C, Paragraph [0024]) on the lower channel pattern (110D);
an upper gate electrode (upper section of "metal gate," (130B); Fig. 2C, Paragraph [0024]) on the upper channel pattern (110C);
an interlayer dielectric layer ("dielectric layer," (125); Paragraph [0022]) on the upper gate electrode (upper section of 130B) and the upper source/drain pattern (120A);
a lower active contact ("source/drain contact," (180A); Paragraph [0035]) that penetrates the substrate (100) and is electrically connected to the lower source/drain pattern (120B);
an upper active contact ("source/drain contact," (150C); Paragraph [0032]) that penetrates the interlayer dielectric layer (125) and is electrically connected to the upper source/drain pattern (120A),
the upper active contact (150C) including a first portion that vertically overlaps at least part of the lower active contact (180A) and at least part of a second portion other than the first portion (Fig. 2A shows the top of the semiconductor device including 150C and Fig. 2B shows the bottom of the semiconductor device including 180A. The upper contact clearly extends beyond the region marked '15' whereas the lower contact does not);
a backside metal layer ("backside routing structure," (148B); Paragraph [0031]) on the second surface (backside) of the substrate (100), the backside metal layer (148A) including a ground line ("ground voltage, such as Vss," (185A); Paragraph [0035])
a first metal layer ("frontside routing structure," (148A); Paragraph [0031]) on the interlayer dielectric layer (125);
Yang does not explicitly teach wherein the backside metal layer includes a power line,
a first lower via that electrically connects the ground line to the lower active contact; and
a second lower via that electrically connects the power line to the second portion of the upper active contact.
Do teaches a semiconductor memory device comprising at least backside metal layer (layer including power lines P1 and P2) including a power line (“power line,” (P2); Fig. 5A, Paragraph [0024]),
“first power via,” (20_13); Fig. 5A, Paragraph [0055]) that electrically connects the ground line (“first power line […] may be an electrical ground voltage,” (P1); Paragraphs [0024, 0047]) to the lower active contact (“lower routing contact,” (27_L1); Paragraph [0049]); and
a second lower via (“second power via,” (30_3); Paragraph [0050]) that electrically connects the power line (“power line,” (P2); Fig. 5A, Paragraph [0024]) to the second portion of the upper active contact (“upper routing contact,” (27_U1); Paragraph [0050]). (In Do Fig. 5A, it is seen that the second lower via 30_3 extends along the side of the lower active contact 27_L1 in order to contact the upper active contact 27_U1 on a region not overlapping the lower active contact 27_L1, otherwise the via would also contact the lower active contact).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further incorporate the teachings of Do into the device of Yang such that the device includes a first lower via electrically connecting the ground line to the lower active contact and a second lower via electrically connecting the power line to the upper active contact. This is because arranging the lower vias in this manner allows for the power and ground lines to be located on cell boundaries, with vias providing electrical pathways for multiple cells along those boundaries while both decreasing the total amount of space needed and increasing efficiency (Paragraphs [0055, 0003]).
Regarding Claim 18, Yang as modified by Do teaches the device of claim 16, wherein the first metal layer (148A) includes an additional power line ("voltage line," (170C); Fig. 2A, Paragraph [0033]), and the additional power line (170C) is electrically connected through an upper via ("source/drain via," (160C); Fig. 2AParagraph [0032]) to the upper active contact (150C).
Regarding Claim 20, Yang as modified by Do teaches the device of claim 16, wherein the lower active region (LAR) includes an NMOSFET region ("may include […] MOSFET's," Paragraph [0015]; "form portions of n-type transistors," Paragraph [0023]), and the upper active region (UAR) includes a PMOSFET region ("may include […] MOSFET's," Paragraph [0015]; "form portions of p-type transistors," Paragraph [0023]).
Claims 9 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Do and Hong et al. (US 20220109046 A1), hereinafter Hong.
Regarding Claim 9, Yang as modified by Do teaches the device of claim 1,
wherein the lower active region (LAR) includes a first semiconductor pattern ("semiconductor layer," (upper 110D); Paragraph [0020]) and a second semiconductor pattern ("semiconductor layer," (lower 110D); Paragraph [0020]) on the first semiconductor pattern (upper 110D),
the first lower gate electrode (lower section of 130B) at least partly surrounds the first semiconductor pattern (upper 110D) and the second semiconductor pattern (lower 110D),
the upper active region (UAR) includes a third semiconductor pattern ("semiconductor layer," (110C); Paragraph [0020]), and
the first upper gate electrode (upper section of 130B) at least partly surrounds the third semiconductor pattern (110C).
Yang as modified by Do does not explicitly teach a fourth semiconductor pattern on the third semiconductor pattern, and
the first upper gate electrode at least partly surrounds the fourth semiconductor pattern.
Hong teaches a semiconductor memory device (“multi-stack nanosheet structure,” (200A) included in “semiconductor device,” (200B) ; Fig. 2A, Paragraph [0039]) comprising at least a fourth semiconductor pattern (higher of “channel set,” (220); Paragraph [0039]) on the third semiconductor pattern (lower of “channel set,” (220); Paragraph [0039]), and
the first upper gate electrode (“2nd gate structure,” (225); Paragraph [0041]) at least partly surrounds the fourth semiconductor pattern (higher of “channel set,” (220)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Hong into the device of Hang as modified by Do such that the device includes a fourth semiconductor pattern surrounded by a gate electrode. This is because having a plurality of semiconductor patterns within the gate enables more space for connection of source/drain regions across the gate of the transistor Paragraph [0014]).
Regarding Claim 17, Yang as modified by Do teaches the device of claim 16, wherein the lower channel pattern (110D) includes a first semiconductor pattern ("semiconductor layer," (upper 110D); Paragraph [0020]) and a second semiconductor pattern (semiconductor layer," (lower 110D); Paragraph [0020]) on the first semiconductor pattern (upper 110D),
the lower gate electrode (lower section of 130B) at least partly surrounds the first semiconductor pattern (upper 110D) and the second semiconductor pattern (lower 110D),
the upper channel pattern (110C) includes a third semiconductor pattern ("semiconductor layer," (110C); Paragraph [0020]), and
the upper gate electrode (upper section of 130B) at least partly surrounds the third semiconductor pattern (110C).
Yang as modified by Do does not explicitly teach a fourth semiconductor pattern on the third semiconductor pattern, and
the upper gate electrode at least partly surrounds the fourth semiconductor pattern.
Hong teaches a semiconductor memory device (“multi-stack nanosheet structure,” (200A) included in “semiconductor device,” (200B) ; Fig. 2A, Paragraph [0039]) comprising at least a fourth semiconductor pattern (higher of “channel set,” (220); Paragraph [0039]) on the third semiconductor pattern (lower of “channel set,” (220); Paragraph [0039]), and
the upper gate electrode (“2nd gate structure,” (225); Paragraph [0041]) at least partly surrounds the fourth semiconductor pattern (higher of “channel set,” (220)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Hong into the device of Hang as modified by Do such that the device includes a fourth semiconductor pattern surrounded by a gate electrode. This is because having a plurality of semiconductor patterns within the gate enables more space for connection of source/drain regions across the gate of the transistor Paragraph [0014]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Do and Guler et al. (US 20240321685 A1), hereinafter Guler.
Regarding Claim 19, Yang as modified by Do teaches the device of claim 16.
Yang as modified by Do does not explicitly teach a semiconductor memory device, further comprising a cutting structure that cuts the lower gate electrode and the upper gate electrodes,
wherein the cutting structure has a linear shape that extends along the lower active region and the upper active regions, and
wherein the second lower via penetrates the cutting structure.
Guler teaches a semiconductor memory device (“integrated circuit;” Figs. 2A-2J (cross-sectional views of process for forming integrated circuit), Paragraph [0034]) comprising at least a cutting structure (“liner,” (224); Fig. 2J, Paragraph [0052]) that cuts the lower gate electrode (lower part of “gate electrode,” (218); Paragraph [0049]) and the upper gate electrode (upper part of “gate electrode,” (218); Paragraph [0049]),
wherein the cutting structure (224) has a linear shape (Fig. 2J) that extends along the lower active region and the upper active regions, and (224 extends through the entirety of the gate electrode, which implicitly contains an active region being connected to source/drain regions)
wherein the second lower via (“conductive via,” (226); Fig. 2J, Paragraph [0053]) penetrates the cutting structure (224).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Guler into the device of Hang as modified by Do such that the device includes a cutting structure that cuts the upper and lower gate electrodes and a second via penetrates the cutting structure. The cutting structure and via is formed between adjacent devices in order to isolate adjacent gate structures while still allowing contact from backside and frontside metal elements. (Paragraphs [0047, 0053]).
Conclusion
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/NOLAN GABRIEL STUESSY/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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