Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election of Invention I in the reply filed on 02/26/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claims 19-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/26/2026. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claims 5- 7, and 9- 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 5 -7 recite the limitation " the some conducting material where vertically-between the only some " in line 1 of the claim s . There is insufficient antecedent basis for this limitation in the claim and so the claims are unable to be examined on the merits. Claims 9 and 11-12 all recite the limitation " the some conducting material where vertically-between the immediately-vertically-adjacent first tiers " in line 1 of the claims. There is insufficient antecedent basis for this limitation in the claim and so the claims are unable to be examined on the merits. Claim 10 is rejected under 35 U.S.C. 112(b) for being dependent upon a claim rejected under 35 U.S.C. 112(b). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3, 8, 13-15, and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Son et al. (US20110147824A1, hereinafter Son ). Regarding claim 1 , Son discloses a method used in forming memory circuitry, comprising: forming a stack comprising vertically-alternating first tiers and second tiers directly above a conductor tier, the first tiers comprising sacrificial material and the second tiers comprising non-sacrificial material that is of different composition from that of the sacrificial material (Fig. 4D vertically alternating stack of dielectric patterns 121a-126a and sacrificial patterns 112a-116a semiconductor layer 1 ) , the stack comprising horizontally-elongated trenches extending through the first tiers and the second tiers and that are individually between immediately-laterally-adjacent memory-block regions (Fig. 4D, par. 98 second groove 13 “ may have a groove shape ” and extends through the alternating stack of dielectric patterns 121a-126a and sacrificial patterns 112a-116a between a left and right memory region) ; forming channel-material strings that extend through the first and second tiers in the memory-block regions (Fig. 4D active pillars 9 formed through alternating stack of dielectric patterns 121a-126a and sacrificial patterns 112a-116a) ; through the horizontally-elongated trenches, replacing the sacrificial material with conductive material that comprises control-gate lines in the memory-block regions (Figs. 4E-4G sacrificial layers 112a-116a removed and replaced with gate layer 25) ; and after the replacing, forming conducting material in a lowest of the first tiers and that directly electrically couples together the channel material of the channel-material strings and conductor material of the conductor tier (Fig. 4H ground select gate pattern formed in lowest tier and electrically couples together active layer 9 and first impurity implantation region 3) . Regarding claim 2 , Son discloses t he method of claim 1 comprising: after replacing the sacrificial material and before forming the conducting material in the lowest first tier, etching away sacrifice material from the lowest first tier (Fig. 4D lowermost sacrificial layer 111a etched away) ; and replacing the etched sacrifice material with the conducting material and that is directly against sidewalls of the channel material of the channel- material strings (Fig. 4H ground select gate pattern formed in lowest tier and electrically couples together active layer 9 and first impurity implantation region 3) . Regarding claim 3 , Son discloses t he method of claim 1 comprising, after replacing the sacrificial material and before forming the conducting material, forming intervening material in the horizontally-elongated trenches laterally-between and longitudinally-along the immediately-laterally-adjacent memory-block regions, the intervening material comprising: a laterally-outer insulative lining extending through the stack longitudinally-along the immediately-laterally-adjacent memory-block regions (Fig. 4G information storage layer 20 extends through stacks in the memory regions) ; and some of the conducting material, the some conducting material being longitudinally-along the immediately-laterally- adjacent memory-block regions laterally-inward of and directly against the laterally-outer insulative lining, the some conducting material being vertically-between at least some immediately- vertically-adjacent of the first tiers (Fig. 4H portions of the conducting material 25 form ground select gate pattern 25 g in the memory block regions and directly against information storage layer 20) . Regarding claim 8 , Son discloses t he method of claim 3 wherein the some conducting material is vertically-between all of the immediately-vertically-adjacent first tiers (Fig. 4H ground select gate pattern 25g is between the first and second tiers) . Regarding claim 13 , Son discloses t he method of claim 3 wherein the some conducting material is also below the intervening material in the memory blocks and there directly electrically couples together the channel material of the channel- material strings and the conductor material of the conductor tier (Fig. 4H portions of ground select gate pattern 25g lie below information storage layer 20 and directly electrically couple active pillar 9a and first impurity implantation region 3) . Regarding claim 14 , Son discloses the method of claim 1 comprising: forming individual of the first tiers to comprise a control-gate line in individual of the memory-block regions, the control-gate line being recessed laterally-inward of sidewalls of insulative material of the second tiers that are immediately-directly-above and immediately-directly-below the control-gate line and thereby form lateral recesses relative such sidewalls (Figs. 4E-4H lowermost recessed region R1 formed into ground select gate pattern 25g); after replacing the sacrificial material and before forming the conducting material, forming intervening material in the horizontally-elongated trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions, the intervening material comprising: a laterally-outer insulative lining extending through the stack longitudinally-along the immediately-laterally-adjacent memory-block regions, the laterally-outer insulative lining being within and less-than-filling the lateral recesses (Fig. 4G information storage layer 20 extends through stacks in the memory regions) ; and some of the conducting material, the some conducting material being in at least some of the lateral recesses laterally-inward of the laterally-outer insulative lining (Fig. 4H portions of the conducting material 25 form ground select gate pattern 25 g in the memory block regions and directly against information storage layer 20) . Regarding claim 15 , Son discloses t he method of claim 14 wherein the laterally-outer insulative lining is all along floors and ceilings of the at least some lateral recesses in a respective vertical cross-section (Fig. 4G information storage layer 20 is all along floors and ceilings of at least some of the recesses R1) . Regarding claim 1 7 , Son discloses t he method of claim 14 wherein the some conducting material is in all of the lateral recesses (Fig. 4H ground select gate pattern 25g is between the first and second tiers) . Regarding claim 18 , Son discloses t he method of claim 14 wherein the some conducting material less-than-fills remaining volume of the at least some lateral recesses in a respective vertical cross-section (Fig. 4G information storage layer 20 does not fully fill the plurality of recesses R1 and is only on the sidewalls) . Allowable Subject Matter Claim s 4 and 16 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 4 and its dependent claims , the closest prior art ( US20110147824A1 , US20150318301A1 , US10964714B2 ) discloses t he method of claim 3 . However, the closest prior art does not teach in combination with the other claimed elements wherein the some conducting material is vertically-between only some of the immediately-vertically-adjacent first tiers . Additionally, the closest prior art does not teach the above in combination with the further limitations of dependent claims not rejected under 35 U.S.C. 112 . Examiner notes that while there are embodiments within the prior art, see Son fig. 4H , that teach having portions of the conducting material vertically between all of the immediately vertically adjacent first tiers , examiner's search of the prior art did not find an embodiment nor any motivation to combine embodiments such that the some conducting material is vertically-between only some of the immediately-vertically-adjacent first tiers in addition with the other limitations of the independent claim. Regarding claim 16 , the closest prior art ( US20110147824A1 , US20150318301A1 , US10964714B2 ) teaches t he method of claim 14 . However, the closest prior art does not teach in combination with the other claimed elements wherein the some conducting material is in only some of the lateral recesses. Examiner notes that while there are embodiments within the prior art, see Son fig. 4H , that teach having portions of the conducting material vertically between all of the immediately vertically adjacent first tiers , examiner's search of the prior art did not find an embodiment nor any motivation to combine embodiments such that the some conducting material is in only some of the lateral recesses in addition with the other limitations of the independent claim. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT COLE LEON LINDSEY whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-4028 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday - Friday, 8:00 a.m. - 5:00 p.m. . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Christine Kim can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571)272-8458 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /COLE LEON LINDSEY/ Examiner, Art Unit 2812 /CHRISTINE S. KIM/ Supervisory Patent Examiner, Art Unit 2812