DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-10 in the reply filed on June 12, 2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/13/2023 is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Fantini et al. (US 20220051944 A1) in view of Fratin et al. (KR 20200032766 A) and Fratin et al. (KR 20210150607 A).
Regarding claim 1 and 10, Fantini et al. (US 20220051944 A1) teaches a memory device ([0024]) comprising:
a plurality of first conductors (conductive material layers 705) arranged apart from each other and perpendicular (FIG. 13) to a substrate (substrate 104);
a second conductor (conductive pillars 1005) extending perpendicular (FIG. 13) to the substrate;
a chalcogenide layer (data storage element 125(i)) between (FIG. 13) the plurality of first conductors (conductive material layers 705) and the second conductor (conductive pillar 100); and
a plurality of first diffusion barrier layers (barriers 1305) selectively arranged only on (FIG. 13) the plurality of first conductors (conductive material layers 705) between (FIG. 13) the plurality of first conductors and the chalcogenide layer.
Fantini et al. does not teach specifically a chalcogenide layer extending perpendicular to the substrate and
the plurality of first diffusion barrier layers each including a carbon-based material.
However, Fratin et al. (KR 20200032766 A) teaches a chalcogenide layer (chalcogenide alloy 505) extending perpendicular (FIG. 5) to the substrate ([0094], silicon substrate on which memory array 500 is formed). And Fratin et al. (KR 20210150607 A) teaches the plurality of first diffusion barrier layers (storage element material 465) each including a carbon-based material ([0049], combination of chalcogen element sulfur (S) and carbon (C)).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have replaced the chalcogenide layer of Fantini et al. with that of Fratin et al. (KR 20200032766 A), so that it extends perpendicular to the substrate, instead of staggering. Forming a continuous chalcogenide layer down to the substrate ensures uniform conductive path formation, stable interface adhesion, reduced material mixing or diffusion, and increased scalability.
Regarding claim 2, Fantini et al. in view of Fratin et al. (KR 20200032766 A) and Fratin et al. (KR 20210150607 A) teaches the memory device of claim 1. Fantini et al. teaches wherein each of the plurality of first conductors (conductive material layers 705) extends parallel (FIG. 13) to the substrate (substrate 104), and the plurality of first diffusion barrier layers (barriers 1305) are on side surfaces (FIG. 13) of the plurality of first conductors.
Regarding claim 3, Fantini et al. in view of Fratin et al. (KR 20200032766 A) and Fratin et al. (KR 20210150607 A) teaches the memory device of claim 1. Fantini et al. teaches the plurality of first diffusion barrier layers (barriers 1305).
Fantini et al. does not teach wherein each of the plurality of first diffusion barrier layers includes carbon, a carbon nitride, or a compound of carbon and chalcogenide.
However, Fratin et al. (KR 20210150607 A) teaches wherein each of the plurality of first diffusion barrier layers (storage element material 465) includes a compound of carbon and chalcogenide ([0049], combination of chalcogen element sulfur (S) and carbon (C)).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the first diffusion barrier layers of Fantini et al. to have comprised a carbon-chalcogenide compound that Fratin et al. (KR 20210150607 A) uses in their first diffusion barrier layers. Using a carbon-based diffusion barrier, such as carbon-chalcogenide compound, limits metal/chalcogenide mixing.
Regarding claim 4, Fantini et al. in view of Fratin et al. (KR 20200032766 A) and Fratin et al. (KR 20210150607 A) teaches the memory device of claim 1. Fantini et al. teaches the plurality of first conductors (conductive material layers 705) and the second conductor (conductive pillars 1005).
Fantini et al. does not teach wherein the plurality of first conductors and the second conductor each include a metal material.
However, Fratin et al. (KR 20200032766 A) teaches wherein the plurality of first conductors (electrode plane 110-b) and the second conductor (conductive pillars 120-b) each include a metal material ([0021], copper (Cu)).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the first and second conductors of Fantini et al. to have comprised a metal material, such as copper, as taught in Fratin et al. (KR 20200032766 A). Metals, particularly copper, have high electrical conductivity and thus increased efficiency and lower power consumption. Also, area selective deposition on metal surfaces distinguishes metal surfaces from insulating surfaces, and enables barrier placement only where needed so that it doesn’t electrically connect adjacent first conductors and create crosstalk.
Regarding claim 5, Fantini et al. in view of Fratin et al. (KR 20200032766 A) and Fratin et al. (KR 20210150607 A) teaches the memory device of claim 1. Fantini et al. teaches wherein the chalcogenide layer (data storage element 125(i)) includes at least one of a chalcogen element, Ge, As, and Sb ([0051], Ge1Sb2Te4).
Regarding claim 6, Fantini et al. in view of Fratin et al. (KR 20200032766 A) and Fratin et al. (KR 20210150607 A) teaches the memory device of claim 5. Fantini et al. teaches wherein the chalcogenide layer (data storage element 125(i)) includes a GeSbTe-based material ([0051], Ge1Sb2Te4).
Regarding claim 7, Fantini et al. in view of Fratin et al. (KR 20200032766 A) and Fratin et al. (KR 20210150607 A) teaches the memory device of claim 1. Fantini et al. teaches further comprising: a second diffusion barrier layer (barriers 1310) between the chalcogenide layer (data storage element 125(i)) and the second conductor (conductive pillars 1005).
Fantini et al. does not teach wherein the second diffusion barrier layer includes a carbon-based material.
However, Fratin et al. (KR 20200032766 A) teaches wherein the second diffusion barrier layer (electrode cylinder 130-b) includes a carbon-based material ([0021], carbon).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the second diffusion barrier layer of Fantini et al. to have comprised a carbon-based material that Fratin et al. (KR 20210150607 A) uses in their second diffusion barrier layer. Using a carbon-based diffusion barrier, such as carbon, limits metal/chalcogenide mixing.
Regarding claim 8, Fantini et al. in view of Fratin et al. (KR 20200032766 A) and Fratin et al. (KR 20210150607 A) teaches the memory device of claim 7. Fantini et al. teaches wherein the second diffusion barrier layer (barriers 1310) extends perpendicular (FIG. 13) to the substrate (substrate 104).
Regarding claim 9, Fantini et al. in view of Fratin et al. (KR 20200032766 A) and Fratin et al. (KR 20210150607 A) teaches the memory device of claim 1. Fantini et al. teaches further comprising: a plurality of insulating layers (first dielectric material layers 204) between (FIG. 13) the plurality of first conductors (conductive material layers 705).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEANNE M KIM whose telephone number is (571)272-8768. The examiner can normally be reached Monday-Thursday 8:00-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JEANNE MYON KIM/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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