DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of claims 10-21 in the reply filed on 4/9/2026 is acknowledged. The traversal is on the ground(s) that there would be no serious search burden because the device and method overlap in search. This is not found persuasive because the etching or removal process of the method is in a different classification and would require a different field of search. These factors create a search burden.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 10, 15-18 and 20-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by OH (US 20200220049).
Regarding claim 10, OH discloses a light-emitting device, comprising:
a semiconductor stack (the stack 30, see fig 2, para 67), comprising a first side surface (the left side surface of 30 in fig 2);
an electrode (electrode 35b, see fig 2, para 67) formed on the semiconductor stack, comprising a first top surface (the top surface of 35b, see fig 2) and a second side surface (the lower left side surface of 35b which is in direct contact with 33, see fig 2, para 67);
an insulating stack (fig 2, 33, para 81) covering the semiconductor stack (33 covers 30 at least partially, see fig 2) and directly contacting the second side surface (33 directly contacts the side surface of 35b, see fig 2), comprising a plurality of first sub-layers with a first refractive index and a plurality of second sub-layers with a second refractive index alternately stacked (33 can be a DBR with layers of different refractive indices alternately stacked, see para 81); and
an electrode pad (fig 2, 39b, para 67) formed on the insulating stack, connecting to the first top surface (39b is directly in contact with 35b, see fig 2);
wherein the insulating stack comprises a second top surface surrounding the first top surface (the top surface of 33 which extends to either side of and surrounds the top surface of 35b, see fig 1-2) and the second top surface is flush with the first top surface or closer to the semiconductor stack than the first top surface (the top surface of 33 is closer to the top surface of 30 than is the top surface of 35, see fig 2).
Regarding claim 15, OH discloses the light-emitting device according to claim 10, further comprising a protective layer (fig 2, 37, para 40) covering the semiconductor stack;
wherein the protective layer comprises an opening and the electrode is filled in the opening and electrically connected to the semiconductor stack (electrode 35 is in the opening in 37 and is connected to 30, see fig 2).
Regarding claim 16, OH discloses the light-emitting device according to claim 15, further comprising a contact layer (fig 2, 31, para 44) under the protective layer;
wherein the opening is formed on the contact layer (the opening in 37 is at least indirectly on 31, see fig 2) and the electrode is connected to the contact layer (35b is directly connected to 31, see fig 2).
Regarding claim 17, OH discloses the light-emitting device according to claim 10, further comprising a covering layer formed on the insulating stack (the upper insulation layer 37 which is formed on 33, see fig 1-4);
wherein the covering layer comprises a third top surface which has a level lower than or equal to that of the second top surface (there is a top surface of 37 between the two mesas M1 and M2 which is lower than the topmost surface of 33, see fig 3).
Regarding claim 18, OH discloses the light-emitting device according to claim 17, wherein the electrode pad is formed on the third top surface (35 is at least indirectly on the top surface of 37, see fig 3).
Regarding claim 20, OH discloses the light-emitting device according to claim 10, wherein the second top surface comprises top surfaces of the first sub-layers and the second sub-layers (since 33 comprises alternating layers of 33-1 and 33-2, and is etched such that its top surface tapers down gradually towards its bottom surface which will cut diagonally through these layers to form the gaps 33, its top surface will comprise top surfaces of both 33-1 and 33-2, see fig 5 and 6A-B, para 108).
Regarding claim 21, OH discloses the light-emitting device according to claim 10, wherein the insulating stack further comprises a third side surface connecting the first side surface (33 comprises a side surface that is directly in contact with the side surface of 30, see fig 2).
Claim(s) 10-14 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SEO (US 201200774441).
Regarding claim 10, SEO discloses a light-emitting device, comprising:
a semiconductor stack (fig 2, 30, para 41), comprising a first side surface (inner side surface of a trench in 30, see fig 2);
an electrode (the electrode comprising 35a, 39a, 65a and 67a, see fig 2, para 40 and 58) formed on the semiconductor stack, comprising a first top surface (the surface of 65a in direct contact with 69a is an upper surface if the device in fig 2 is turned over, see fig 2) and a second side surface (the side surface of 35a in the trench in 30 which is in direct contact with 33, see fig 2);
an insulating stack (the stack of insulating layers 33, 37, 49 and 61, see fig 2, para 40 and 58) covering the semiconductor stack and directly contacting the second side surface (33 covers portions of 30 and directly contacts the side surface of 35a, see fig 2), comprising a plurality of first sub-layers with a first refractive index and a plurality of second sub-layers with a second refractive index alternately stacked (the stack comprises 33 which can be a DBR, see para 45); and
an electrode pad (fig 2, 69a, para 95) formed on the insulating stack, connecting to the first top surface;
wherein the insulating stack comprises a second top surface (the surface of 61 in direct contact with 69a, see fig 2 ) surrounding the first top surface (61 surrounds 65a, see fig 2) and the second top surface is flush with the first top surface or closer to the semiconductor stack than the first top surface (the surfaces of 65a and 61 which are in contact with 69a are flush, see fig 2).
Regarding claim 11, SEO discloses the light-emitting device according to claim 10, wherein a level difference between the first top surface and the second top surface is less than 0.5 um (the surfaces of 65a and 61 which are in contact with 69a are flush, see fig 2).
Regarding claim 12, SEO discloses the light-emitting device according to claim 10, wherein:
the semiconductor stack comprises a first semiconductor layer (layer 25, see fig 2, para 41) and a mesa (the mesa comprising 27 and 29 on 25, see fig 2, para 41) on the first semiconductor layer, the mesa includes a second semiconductor layer (fig 2, 29, para 41) and the first semiconductor layer comprises an exposed region not covered by the mesa (there is a region of 25 between the mesas that is therefore not covered by the mesa, see fig 2);
the electrode is formed on the exposed region (35 is in direct contact with 25 between the mesas, see fig 2) and has a thickness greater than a height of the mesa (35 is thicker than the height of 27 and 29, see fig 1).
Regarding claim 13, SEO discloses the light-emitting device according to claim 10, wherein:
the semiconductor stack comprises a first semiconductor layer (layer 25, see fig 2, para 41) and a mesa (the mesa comprising 27 and 29 on 25, see fig 2, para 41) on the first semiconductor layer, the mesa includes a second semiconductor layer (fig 2, 29, para 41) and the first semiconductor layer comprises an exposed region not covered by the mesa (there is a region of 25 between the mesas that is therefore not covered by the mesa, see fig 2);
the electrode comprises a first electrode (the electrode comprising 35, 29a, 67a and 65a that is on 25 between the mesas, see fig 2, para 58) on the exposed region and a second electrode (the electrode comprising 39b, 67b and 65b that is on the mesa, see fig 2, para 58) on the mesa, and the thickness of the first electrode is greater than the thickness of the second electrode (the total thickness of 35, 39a, 67a and 65a is greater than the total thickness of 39b, 67b and 65b, see fig 2).
Regarding claim 14, SEO discloses the light-emitting device according to claim 13, wherein a level difference between a top surface of the first electrode and a top surface of the second electrode is less than 0.5 um (the top surfaces of 65a and 65b are level, see fig 2).
Regarding claim 19, SEO discloses the light-emitting device according to claim 10, wherein the electrode pad covers and contacts the second top surface (69a is in direct contact with and at least partially covers the top surface of 61, see fig 2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/LYNNE A GURLEY/Supervisory Patent Examiner, Art Unit 2811
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