DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The status of the claims is as follows:
Claims 1-8, 12-18 have been elected.
Claims 9-11, 19-20 have been withdrawn.
An action on the merits for claims 1-8, 12-18 follows.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). However, should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)- (d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non- English application.
IDS
All references provided in the IDS have been considered.
Election/Restriction
Applicant’s election without traverse of the invention corresponding to claims 1-8, 12-18 in the reply filed on 12/14/2023 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Display Apparatus Comprising Multi-Layered Light Absorption Layer.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4, and 14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4 of U.S. PGPUB No. US20240258333A1 (Currently amended claims of Application 18/541,085 filed 08/05/2026 are used herein). Although the claims at issue are not identical, they are not patentably distinct from each other because they recite the scope of the referenced application fully anticipates the same scope of subject matter of these claims of the present application.
Instant Application 18/540,471
Reference Patent Application 18/541,085
A display apparatus, comprising:
a display panel including a first substrate and a second substrate;
a color filter layer disposed on the first substrate;
a plurality of gate lines and a plurality of data lines disposed on the second substrate to define a plurality of subpixels;
a thin film transistor disposed in each of the plurality of subpixels on the second substrate;
a common electrode and a pixel electrode disposed in each of the plurality of subpixels; and
a light absorption layer disposed below each data line to absorb light incident from outside.
A display apparatus, comprising:
a display panel including a first substrate and a second substrate;
a backlight unit facing the first substrate and configured to supply light to the display panel;
a color filter layer on the first substrate;
a plurality of gate lines and data lines on the second substrate configured to form a plurality of sub-pixels;
a thin film transistor in each of the plurality of sub-pixels on the second substrate;
a pixel electrode and a common electrode in each of the plurality of sub-pixels;
a common line on the second substrate to apply an signal to the common electrode; and
a light shielding layer under the common line,
(the light shielding layer functions as a light absorption layer because both reduce external light entering the inside of the device)
wherein the light shielding layer includes a first light shielding layer configured to absorb the light and a second light shielding layer made of a metal.
The display apparatus of claim 1, wherein the light absorption layer includes:
a first metal layer having an extinction coefficient (k), where 0.6<k<1.2; and
a second metal layer disposed on the first metal layer.
1. […] wherein the light shielding layer includes a first light shielding layer configured to absorb the light and a second light shielding layer made of a metal.
2. The display apparatus of claim 1, wherein the first light shielding layer is formed of material having an extinction coefficient (K) of 0.6<k<1.2.
3. The display apparatus of claim 2, wherein the first metal layer includes a composite material composed of a metal and a ceramic material.
3. The display apparatus of claim 2, wherein the first light shielding layer is formed of a composite material of the metal and a ceramic material.
4. The display apparatus of claim 3, wherein the metal of the first metal layer includes Mo or MoOx, and wherein the ceramic material of the first metal layer includes Nb2O5.
4. The display apparatus of claim 3, wherein the metal of the first light shielding layer includes Mo or MoOx, and the ceramic material of the first light shielding layer includes Nb2O5.
14. The display apparatus of claim 1, further comprising:
a backlight unit facing the first substrate and configured to supply light to the display panel.
1. A display apparatus, comprising:
[…]
a backlight unit facing the first substrate and configured to supply light to the display panel;
[…]
Claim Rejections - 35 USC § 102
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ahn (US 20060139552 A1).
Regarding Claim 1, Ahn teaches a display apparatus ("display device;" Figs. 2 (plan view), 3 & 5 (sectional views), 6a & 6b (fabrication step), Paragraph [0003], comprising:
a display panel ("liquid crystal display panel;" Fig. 5, Paragraph [0028]) including a first substrate ("color filter substrate," (210); Fig. 5, Paragraph [0050]) and a second substrate ("lower substrate," (150); Fig. 3, Paragraph [0036]);
a color filter layer ("color filter," (6); Fig. 1, Paragraph [0007]: in discussion of related art in Paragraph [0007] it is taught that a color filter substrate generally includes a color filter. Therefore, the color filter substrate of Fig. 5 includes a color filter) disposed on the first substrate (210);
a plurality of gate lines ("gate line," (102); Fig. 2, Paragraph [0036]) and a plurality of data lines ("data line," (104); Fig. 2, Paragraph [0036]) disposed on the second substrate (150) to define a plurality of subpixels ("pixel area;" Paragraph [0036]);
a thin film transistor ("thin film transistor, (TFT); Paragraph [0036]) disposed in each of the plurality of subpixels ("pixel area") on the second substrate (150);
a common electrode ("common electrode," (122); Paragraph [0036]) and a pixel electrode ("pixel electrode," (118); Paragraph [0036]) disposed in each of the plurality of subpixels ("pixel area"); and
a light absorption layer ("data link," (135); Fig. 3, Paragraph [0046]) disposed below each data line (104) to absorb light incident from outside.
Regarding Claim 15, Ahn teaches a display apparatus ("thin film transistor substrate" of a display; Figs. 2 (plan view), 3 (sectional views), 6a, 6b (method of making), Paragraph [0035]), comprising:
a substrate ("lower substrate," (150); Fig. 3, Paragraph [0036]) including a subpixel region ("pixel area;" Paragraph [0036]) and a pad region (area outside the subpixel region and including pads) adjacent to the subpixel region ("pixel area");
a subpixel ("pixel;" Paragraph [0040]) disposed in the subpixel region ("pixel area");
a light absorption layer ("data link," (135); Figs. 2, 3, Paragraph [0046]) and a gate electrode ("gate electrode extended from the gate line," (102); Paragraph [0039]) of the subpixel ("pixel") separated from each other, and disposed in the subpixel region ("pixel area") of the substrate (150);
a data line ("data line," (104); Fig. 3, Paragraph [0036]) disposed on the light absorption layer (135); and
a gate pad ("gate pad electrode," (126); Paragraph [0045]) separated from the light absorption layer (135), and disposed in the pad region (area outside the subpixel region) of the substrate (150), wherein the gate electrode (102), the light absorption layer (135) and the gate pad (126) are formed of a same material in a same process ("formed on the lower substrate;" Figs. 6a, 6b, Paragraph [0053]), and
wherein each of the gate electrode (102), the light absorption layer (135) and the gate pad (126) includes a first metal layer ("first conductive layer," (101); Fig. 3, Paragraph [0038]) and a second metal layer ("second conductive layer," (103); Fig. 3, Paragraph [0038]) disposed on the first metal layer (101).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Ahn in view of Fujikawa et al. (US 5592317 A), hereinafter Fujikawa. (Note: unless otherwise stated, all following reference items and paragraphs refer to Ahn).
Regarding Claim 2, Ahn teaches the display apparatus of claim 1, wherein the light absorption layer (135) includes:
a first metal layer ("first conductive layer," (101); Fig. 3, Paragraph [0038]) and;
a second metal layer ("second conductive layer," (103); Fig. 3, Paragraph [0038]) disposed on the first metal layer (101).
Ahn does not explicitly teach the first metal layer having an extinction coefficient (k), where 0.6<k<1.2.
Fujikawa teaches at least a light absorption layer (“chromium blank;” Fig. 1, Col. 3, Lines 20-25) comprising:
A first metal layer (“second antireflection film,” (130); Fig. 1, Col. 6, Line 1-4) having an extinction coefficient (k), where 0.6<k<1.2. (“extinction coefficient […] =1.1;” Col.6, Lines 1-4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further incorporate the teachings of Fujikawa into the apparatus of Ahn such that the first metal layer is formed of a material having an extinction coefficient between 0.6 and 1.2. Having an intermediate value extinction coefficient, neither a particularly large or particularly small value, within the claimed range allows the second antireflection film’s extinction coefficient to be between the extinction coefficient of the layers on either side of it. This increase of extinction coefficient between layers (and therefore increase in index of refraction) reduces the overall quantity of light reaching the substrate by reflecting light at different points so that it destructively interferes. This has the benefit of suppressing the reflection of exterior light towards the device, improving visibility (Col. 6, Lines 20-43).
Claims 3, 4, 6, 12, and, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn in view of Fujikawa and Chang et al. (US 20210080822 A1), hereinafter Chang
Regarding Claim 3, Ahn as modified by Fujikawa teaches the display apparatus of claim 2.
Ahn as modified by Fujikawa does not explicitly teach wherein the first metal layer includes a composite material composed of a metal and a ceramic material.
Chang teaches at least an analogous device with components for absorbing light (Paragraph [0045]):
wherein the first metal layer (“light blocking layer,” (120); Fig. 1A, Paragraph [0046]) includes a composite material composed of a metal (“Mo;” Paragraph [0046]) and a ceramic material (“Nb2O5;” Paragraph [0046]). (Note: the light blocking layer (120) may be formed of a combination of Mo and Nb2O5 within one layer, thereby being a composite material, Paragraph [0046].)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further incorporate the teachings of Chang into the invention of Ahn and Fujikawa such that the light absorption layer is formed of a composite material of a metal and a ceramic material. Forming the first light shielding layer out of a composite material of a metal and ceramic material realizes a low transmittance value of the light shielding layer ranging from 0% to 18%. This has the benefit of reducing the amount of light that passes through to a small percentage which would improve visibility in the device (Paragraphs [0045] and [0047]).
Regarding Claim 4, Ahn as modified by Fujikawa and Chang further teaches the display apparatus of claim 3, wherein the metal of the first metal layer (Chang, (120)) includes Mo or MoOx (Chang, “Mo;” Paragraph [0046]), and
wherein the ceramic material of the first metal layer (Chang, (120)) includes Nb2O5 (Chang, “Nb2O5;” Paragraph [0046]).
Regarding Claim 6, Ahn as modified by Fujikawa and Chang teaches the display apparatus of claim 4, wherein the thin film transistor (TFT) includes:
a gate electrode ("gate electrode extended from the gate line," (102); Fig. 3, Paragraph [0039]) disposed on the second substrate (150);
a gate insulating layer ("gate insulating film," (152); Paragraph [0036]) disposed on the gate electrode (102);
a semiconductor layer ("active layer," (114); Paragraph [0039]) disposed on the gate insulating layer (152); and
a source electrode ("source electrode," (110); Paragraph [0039]) and a drain electrode ("drain electrode," (112); Paragraph [0039]) disposed on the semiconductor layer (114).
Regarding Claim 12, Ahn as modified by Fujikawa and Chang teaches the display apparatus of claim 4, further comprising: a pad region (area outside the pixel area; Fig. 2) disposed adjacent to the subpixel and including a gate pad ("gate pad electrode," (126); Fig. 2, Paragraph [0036]) and a data pad ("data pad," (132); Fig. 2, Paragraph [0036]).
Regarding Claim 13, Ahn as modified by Fujikawa and Chang teaches the display apparatus of claim 12, wherein the gate pad (124) is formed of a same material ("first conductive layer and second conductive layers," (101, 103); Fig. 3, Paragraph [0048]) as the light absorption layer (135).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn in view of Fujikawa and Chang, and further in view of Wu et al. (US 20150155305 A1), hereinafter Wu.
Regarding Claim 7, Ahn as modified by Fujikawa and Chang teaches the display apparatus of claim 6.
Ahn as modified by Fujikawa and Chang does not explicitly teach wherein the gate insulating layer is excluded in a region where the data line is formed.
Wu teaches at least a display apparatus (“array substrate […] to implement display;” Fig. 11, Paragraph [0131, 0133]), wherein the gate insulating layer (“gate insulating layer,” (7); Paragraph [0131]) is excluded in a region where the data line (“data line,” (4); Paragraph [0136]) is formed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Wu into the device of Ahn such that the gate insulating layer is not covering the light absorption layer. Excluding the gate insulating layer from a region including the data line makes at least a portion of the data line directly exposed to external connection to a circuit board without need for a via, decreasing a contact resistance between the data line and circuit board, and reducing power consumption of the device (Paragraph [0136]).
Regarding Claim 8, Ahn as modified by Fujikawa, Chang, and Wu teaches the display apparatus of claim 7, wherein the data line (104) is disposed directly on an upper surface of the light absorption layer (135; Fig. 3).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Ahn in view of Yamazaki et al. (US 6690434 B1), hereinafter Yamazaki.
Regarding Claim 5, Ahn teaches the display apparatus of claim 1.
Ahn does not explicitly teach wherein the light absorption layer is in a floating state.
Yamazaki teaches at least a display apparatus (“display device;” Figs. 1 (plan view), 2 (sectional view), Col. 4, Lines 40-45) wherein the light absorption layer (“shielding film,” (105); Col. 4, Lines 55-60) is in a floating state (“in a floating state;” Col. 4, Lines 65-67).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Yamazaki into the device of Ahn such that the light absorption layer is in a floating state. Keeping the light absorption layer in a floating state allows it to continue functioning as a storage electrode with the added benefit of forming a more distinct image display with better contrast (Col. 6, Lines 25-51) and reducing manufacturing complexity (Col. 6, Lines 52-62).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Ahn in view of Kim et al. (KR 20150027683A), hereinafter Kim.
Regarding Claim 14, Ahn teaches the display apparatus of claim 1.
Ahn does not explicitly teach a backlight unit facing the first substrate and configured to supply light to the display panel.
Kim teaches a display apparatus (“liquid crystal display device,” (100); Fig. 2, Paragraph [0032]), comprising at least: a backlight unit (110) facing the first substrate (“color filter substrate,” (120)) and configured to supply light to the display panel (“liquid crystal panel,” (DP)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the backlight unit of Kim into the display apparatus of Ahn in order to supply light to the display panel. This is because including a backlight provides the necessary light needed to form an image on a liquid crystal display panel (Paragraphs [0005] and [0032]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Ahn in view of Chang.
Regarding Claim 16, Ahn teaches the display apparatus of claim 15.
Ahn does not explicitly teach wherein the first metal layer includes a composite material composed of a metal and a ceramic material.
Chang teaches at least an analogous device with components for absorbing light (Paragraph [0045]):
wherein the first metal layer (“light blocking layer,” (120); Fig. 1A, Paragraph [0046]) includes a composite material composed of a metal (“Mo;” Paragraph [0046]) and a ceramic material (“Nb2O5;” Paragraph [0046]). (Note: the light blocking layer (120) may be formed of a combination of Mo and Nb2O5 within one layer, thereby being a composite material, Paragraph [0046].)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further incorporate the teachings of Chang into the invention of Ahn and Fujikawa such that the light absorption layer is formed of a composite material of a metal and a ceramic material. Forming the first light shielding layer out of a composite material of a metal and ceramic material realizes a low transmittance value of the light shielding layer ranging from 0% to 18%. This has the benefit of reducing the amount of light that passes through to a small percentage which would improve visibility in the device (Paragraphs [0045] and [0047]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Ahn in view of Murakami et al. (US 20020190256 A1), hereinafter Murakami.
Regarding Claim 17, Ahn teaches the display apparatus of claim 15.
Ahn does not explicitly teach wherein a thickness of the first metal layer is about 4000 - 6000Å, and a thickness of the second metal layer is about 300 - 500Å.
Murakami teaches at least a display apparatus (“pixel section;” Figs. 2, 3 (methods of preparing a pixel section), Paragraph [0075]) wherein a thickness of the first metal layer (“laminated structure;” Paragraph [0076]) is about 4000 - 6000Å (“thickness of 500 nm;” Paragraph [0076]), and a thickness of the second metal layer (“having two layers or more;” Paragraph [0076]) is about 300 - 500Å (“thickness of 50 nm;” Paragraph [0076]). (While Murakami primarily states this thickness with respect to a laminated structure of the gate electrode, (105), it would follow to apply this to the one material used for all components made up of a first and second metal layer as shown in Ahn).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Murakami into the device of Ahn such that a thickness of the first metal layer is about 4000 - 6000Å, and a thickness of the second metal layer is about 300 - 500Å. This provides a suitable height to use the metal layers as a mask for doping of a lower region (Paragraph [0077]) and a desirable thickness of the gate electrode, improving efficiency (Paragraph [0076]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Ahn in view of Wu.
Regarding Claim 18, Ahn teaches the display apparatus of claim 15, further comprising: a gate insulating layer (“gate insulating film,” (152); Fig. 3, Paragraph [0036]) covering the gate electrode (102) and the gate pad (126),
Ahn does not explicitly teach a gate insulating layer not covering the light absorption layer.
Wu teaches at least a display apparatus (“array substrate […] to implement display;” Fig. 11, Paragraph [0131, 0133]) comprising a gate insulating layer (“gate insulating layer,” (7); Paragraph [0131]) not covering the light absorption layer (“transparent conductive layer,” (13); Fig. 11, Paragraph [0131]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Wu into the device of Ahn such that the gate insulating layer is not covering the light absorption layer. Excluding the gate insulating layer from the light absorption layer disposed under the data line provides at least a portion of the data line directly exposed to external connection to a circuit board, decreasing a contact resistance between the data line and circuit board, and reducing power consumption of the device (Paragraph [0136]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nolan Stuessy whose telephone number is (571) 645-5843. The examiner can normally be reached on M-F; 9:00-5:00 (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at https://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NOLAN GABRIEL STUESSY/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812