Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18540482 filed on 12/14/2023.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-21 are rejected under 35 U.S.C. 103 as being unpatentable over Mitsuhira et al. (US 7,858,490).
Regarding Independent claim 1, Mitsuhira et al. teach an electronic circuit including
at least one transistor cell (Fig. 13, elements memory cell area and peripheral circuit area), wherein said at least one transistor cell comprises:
a plurality of transistors (Fig. 13, elements 9a-9g) arranged inside and on top of a semiconductor substrate (Fig. 13, element 1),
each transistor of said plurality of transistors comprising an active area (Fig. 13, area of substrate where transistors 9a-9g are located);
first insulating regions (Fig. 13, elements 6b) at least partially located around each transistor of said plurality of transistors and extending down to a first depth (Fig. 13, element d1) in the semiconductor substrate;
second insulating regions (Fig. 13, element 6c, although Fig. 13 does not explicitly disclose more than one second insulating region it would be obvious to one of ordinary skill in the art that there would be multiple memory cell areas and periphery circuit areas whereby multiple second insulating regions would be in between) positioned to insulate the active areas of the transistors of the plurality of transistors from one another, each second insulating region extending from a bottom of the first insulating region down to a second depth (Fig. 13, element d2) in the semiconductor substrate, the second depth being greater than the first depth (Fig. 13).
Regarding claim 3, Mitsuhira et al. teach wherein the first distance is greater than or equal to 400 nm (specification discloses 100-500 nm) and the second distance is less than or equal to 350 nm (specification discloses 200 nm).
Regarding claim 4, Mitsuhira et al. teach wherein the first insulating regions are shallow trench insulations, and the second insulating regions are deep trench insulations (Fig. 13).
Regarding claim 5, Mitsuhira et al. teach wherein the second insulating regions extend along a first direction substantially parallel to a longitudinal direction of the active areas (Fig. 13).
Regarding claim 6, Mitsuhira et al. teach further comprising third insulating regions (although Fig. 13 does not explicitly disclose third insulating regions it would be obvious to one of ordinary skill in the art that there would be multiple memory cell areas and periphery circuit areas whereby multiple second/third insulating regions (second and third insulating regions are interpreted to be the same isolation structures) would be in between) positioned to insulate the active areas of the plurality of transistors from other transistor cells, each third insulating region extending from the bottom of the first insulating region down to a third depth (the third depth is the same as the second depth) in the semiconductor substrate, the third depth being greater than the first depth.
Regarding claim 7, Mitsuhira et al. teach wherein the third depth is equal to the second depth (Fig. 13, the third depth is the same as the second depth).
Regarding claim 8, Mitsuhira et al. teach wherein the third insulating regions are deep trench insulations (Fig. 13).
Regarding claim 9, Mitsuhira et al. teach wherein the third insulating regions extend along a second direction substantially parallel to a transverse direction of the active areas (Fig. 13).
Regarding claim 10, Mitsuhira et al. teach wherein the first depth is in a range from 250 to 450 nm (specification discloses 100-500 nm), and a difference between the third depth and the first depth is greater than or equal to 100 nm (specification discloses 200 nm).
Regarding claim 11, Mitsuhira et al. teach wherein the transistors of the plurality of transistors are configured for operation at voltages greater than or equal to 10 volts (This is an intended use recitation. The examiner notes that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. See, e.g., In re Schreiber, 128 F.3d 1473, 1477, 44 USPQ2d 1429, 1431 (Fed. Cir. 1997); In re Otto, 136 USPQ 458,459 (CCPA 1963)).
Regarding claim 12, Mitsuhira et al. teach wherein the transistor cell further comprises a gate structure of floating-gate type (specification discloses in Fig. 16 “A control gate electrode (upper electrode) implemented by a polysilicon film 111 and a tungsten silicide film 112 (second conductive film) is formed on the floating gate electrode. In addition, on the surface of silicon substrate 101, a low-concentration impurity region 114a and a high-concentration impurity region 114b serving as a drain region of the memory cell transistor and a source region 115 are formed”) extending above the active areas of the plurality of transistors between a source region and a drain region of each active area.
Regarding claim 13, Mitsuhira et al. teach wherein said electronic circuit is contained in an electrically erasable and programmable non-volatile memory (This is an intended use recitation. The examiner notes that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. See, e.g., In re Schreiber, 128 F.3d 1473, 1477, 44 USPQ2d 1429, 1431 (Fed. Cir. 1997); In re Otto, 136 USPQ 458,459 (CCPA 1963)).
Regarding claim 14, Mitsuhira et al. teach wherein the transistors of the plurality of transistors form switching transistors of a switching circuit Fig. 13, transistors in peripheral circuit area) coupled to memory cells (transistors of memory cell) of a non-volatile memory.
Regarding claim 15, Mitsuhira et al. teach wherein the first depth is in a range from 250 to 450 nm (specification discloses 100-500 nm), and a difference between the second depth and the first depth is greater than or equal to 100 nm (specification discloses 200 nm).
Regarding Independent claim 16, Mitsuhira et al. teach a method of manufacturing an electronic circuit, comprising
at least one transistor cell (Fig. 13, elements memory cell area and peripheral circuit area), each transistor cell comprising
a plurality of transistors (Fig. 13, elements 9a-9g) formed inside and on top of a semiconductor substrate (Fig. 13, element 1),
each transistor of said plurality of transistors comprising an active area (Fig. 13, area of substrate where transistors 9a-9g are located), the method comprising:
forming first insulating regions (Fig. 13, elements 6b) at least partially located around the transistors and extending down to a first depth (Fig. 13, element d1) in the semiconductor substrate; and
forming second insulating regions (Fig. 13, element 6c, although Fig. 13 does not explicitly disclose more than one second insulating region it would be obvious to one of ordinary skill in the art that there would be multiple memory cell areas and periphery circuit areas whereby multiple second insulating regions would be in between) positioned to insulate the active areas of the transistors of the plurality of transistors from one another, each second insulating region extending down from a bottom of the first insulating region to a second depth (Fig. 13, element d2) in the semiconductor substrate, the second depth being greater than the first depth (Fig. 13).
Regarding claim 17, Mitsuhira et al. teach forming third insulating regions (although Fig. 13 does not explicitly disclose third insulating regions it would be obvious to one of ordinary skill in the art that there would be multiple memory cell areas and periphery circuit areas whereby multiple second/third insulating regions (second and third insulating regions are interpreted to be the same isolation structures) would be in between) positioned to insulate the active areas of the plurality of transistors from other transistor cells, each third insulating region extending down from the bottom of the first insulating region to a third depth (the third depth is the same as the second depth) in the semiconductor substrate, the third depth being greater than the first depth.
Regarding claim 18, Mitsuhira et al. teach wherein the third depth is equal to the second depth (Fig. 13, the third depth is the same as the second depth).
Regarding claim 19, Mitsuhira et al. teach wherein the first depth is in a range from 250 to 450 nm (specification discloses 100-500 nm), and a difference between the third depth and the first depth is greater than or equal to 100 nm (specification discloses 200 nm).
Regarding claim 20, Mitsuhira et al. teach wherein the first depth is in a range from 250 to 450 nm (specification discloses 100-500 nm), and a difference between the second depth and the first depth is greater than or equal to 100 nm (specification discloses 200 nm).
Regarding claim 21, Mitsuhira et al. teach an integrated circuit (Fig. 13) comprising an electronic circuit according to claim 1.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Mitsuhira et al. (US 7,858,490) in view of Liaw (US 2025/0087551).
Regarding claim 2, Mitsuhira et al. teach wherein the plurality of transistors of said at least one transistor cell comprise first transistors having active areas separated by a first distance (transistors in memory cell area) and insulated from one another by at least the first insulating regions, and second transistors having active areas separated by a second distance (transistors in peripheral circuit area) and insulated from one another by at least the second insulating regions (Fig. 13).
Mitsuhira et al. do not explicitly disclose a second distance shorter than the first distance.
Liaw teaches a memory device comprising first and second gate structure with the second gate structure having a different gate pitch than the first gate pitch (abstract). Accordingly, the gate pitch is an art recognized variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the gate pitch and arrive at claim 2 limitation. Furthermore, the applicant has not presented persuasive evidence that the claimed pitch is for a particular purpose that is critical to the overall claimed invention
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
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/SHAHED AHMED/
Primary Examiner, Art Unit 2813