Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the Group I invention (a device) and Species B1 (reading on Figs. 2 and 8A-8D in the reply filed on 7/2/2026 is acknowledged.
Claims 19-25 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/2/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/15/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5-15, and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Su (US 20170133351 A1).
Regarding claim 1, Su discloses a package (Fig. 12) comprising:
a first integrated device (one of 234);
a first metallization portion (92/94) coupled to the first integrated device;
an interposer (one of 34; [0019]: “may act as the electrical connections for interconnecting the conductive features overlying and underlying device dies”, thus this structure performs the function of “an interposer”) coupled to the first metallization portion;
a passive device (another of 34; [0019]: “such as active devices or passive devices”) coupled to the first metallization portion;
a plurality of post interconnects (32; [0019]: “or may) be formed”) coupled to the first metallization portion;
a second integrated device (58) coupled to the interposer, the passive device and the plurality of post interconnects (each of these electrical connections are explicitly illustrated through at least one electrical path); and
an encapsulation layer (48) located between (vertically “between”, See annotated figure for direction designation) the first integrated device and the second integrated device.
Illustrated below is a marked and annotated figure of Fig. 12 of Su.
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Regarding claim 2, Su discloses the package of claim 1 (Fig. 12), wherein the encapsulation layer at least partially encapsulates (laterally “encapsulates”, See annotated figure for direction designation) the interposer, the passive device, and the plurality of post interconnects.
Regarding claim 5, Su discloses the package of claim 1 (Fig. 12), wherein the first integrated device comprises a first front side (Side B, See annotated figure) and a first back side (Side A, See annotated figure); and wherein the second integrated device comprises a second front side (one of Side C or Side D, See annotated figure) and a second back side (another of Side C or Side D, See annotated figure).
Regarding claim 6, Su discloses the package of claim 5 (Fig. 12), wherein the first front side of the first integrated device is pointed in a direction (vertical “direction”, See annotated figure) towards the second integrated device.
Regarding claim 7, Su discloses the package of claim 5 (Fig. 12), wherein the first front side of the first integrated device is pointed in a direction (vertical “direction”, See annotated figure) towards the second back side of the second integrated device (Side C).
Regarding claim 8, Su discloses the package of claim 5 (Fig. 12), wherein the first front side of the first integrated device is pointed in a direction towards (vertical “direction”, See annotated figure) the second front side of the second integrated device (Side C).
Regarding claim 9, Su discloses the package of claim 1 (Fig. 12), wherein the first metallization portion is located between (vertically “between”) the first integrated device and the interposer.
Regarding claim 10, Su discloses the package of claim 9 (Fig. 12), further comprising a second metallization portion (50/52) located between (vertically “between”) the second integrated device and the interposer.
Regarding claim 11, Su discloses the package of claim 10, wherein the encapsulation layer is located between (vertically “between”) the first metallization portion and the second metallization portion.
Regarding claim 12, Su discloses the package of claim 10 (Fig. 12), further comprising a third metallization portion (68/70) coupled to the second integrated device.
Regarding claim 13, Su discloses the package of claim 10 (Fig. 12) wherein the first metallization portion comprises:
at least one first dielectric layer (94; [0039]: “dielectric layers”); and
a first plurality of metallization interconnects (92; [0039]: “RDLs”); and
wherein the second metallization portion comprises:
at least one second dielectric layer (50; [0050]: “dielectric layers”); and
a second plurality of metallization interconnects (52; [0039]: “RDLs”).
Regarding claim 14, Su discloses the package of claim 10 (Fig. 12), wherein the first integrated device is coupled to the interposer and the passive device through at least the first metallization portion (at least indirectly physically “coupled”), and wherein the second integrated device is coupled to the interposer and the passive device through at least the second metallization portion (at least indirectly physically “coupled”).
Regarding independent claim 15, Su discloses a package (Fig. 12) comprising:
a first integrated device (one of 234);
an interposer (one of 34; [0019]: “may act as the electrical connections for interconnecting the conductive features overlying and underlying device dies”, thus this structure performs the function of “an interposer”) coupled to the first integrated device (at least indirectly physically “coupled”);
a passive device (another of 34; [0019]: “such as active devices or passive devices”) coupled to the first integrated device (at least indirectly physically “coupled”);
a plurality of post interconnects (32; [0019]: “or may) be formed”) coupled to the first integrated device (each of these electrical connections are explicitly illustrated through at least one electrical path);
a second integrated device (58);
a first metallization portion (50/52) located between (vertically “between”, See annotated figure for direction designation) the second integrated device and the interposer,
wherein the first metallization portion is coupled to the second integrated device, the interposer, the passive device and the plurality of post interconnects (each of these electrical connections are explicitly illustrated through at least one electrical path); and
an encapsulation layer (48) located between (vertically “between”) the first integrated device and the second integrated device.
Regarding claim 17, Su discloses the package of claim 15 (Fig. 12), further comprising:
a second metallization portion (68/70) coupled to (this electrical connection is explicitly illustrated through at least one electrical path) a first side of the second integrated device (Side D, See annotated figure); and
a third metallization portion (92/94) coupled to (this electrical connection is explicitly illustrated through at least one electrical path) the first integrated device, and
wherein the first metallization portion is coupled to (at least indirectly physically “coupled”) a second side of the second integrated device (Side C, See annotated figure).
Regarding claim 18, Su discloses the package of claim 17 (Fig. 12), further comprising:
a second encapsulation layer (66) located between (vertically “between”) the first metallization portion and the second metallization portion; and
a third encapsulation layer (90) coupled to the third metallization portion,
wherein the encapsulation layer (cited in the claim 15 rejection as layer 48, repeated here) is located between (vertically “between”) the second metallization portion and the third metallization portion.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference (or combination of references), but are disclosed or rendered obvious by secondary references or remarks.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Su as applied to claim 1 above, and further in view of Chen (US 20230260977 A1).
Su discloses the package of claim 1 (Fig. 12), wherein the passive device includes a deep trench capacitor ([0018]: “includes…passive devices” with [0019]: “passive devices…capacitors”).
Su teaches the passive device bot only teaches a generic capacitor for this structure. Thus, Su fails to teach “wherein the passive device includes a deep trench capacitor”.
Chen discloses wherein the passive device (Fig. 1A: device 104A) includes a deep trench capacitor (128; [0039]: “Trench capacitors”). Modifying the capacitor (of Su) to be “a deep trench capacitor” (of Chen) would arrive at the claimed capacitor configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the capacitor is sandwiched between metallization portions (Su: Fig. 12: portions 92/94 and 50/52; Chen: Fig. 1A: portions 110 and 106). Chen provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the claimed capacitor configuration in that it would enhance electrical performance of the device during operation while enabling a compact device ([0039]: “performance …can be improved without compromising the size of 3DIC die package”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed capacitor configuration because it would enhance electrical performance of the device while enabling a compact device. MPEP 2143 (I)(G).
Regarding claim 4, Su discloses the package of claim 1 (Fig. 12), wherein the interposer comprises: a silicon substrate (36; [0019]: “semiconductor substrates”); and a plurality of interposer interconnects (42).
Su teaches the interposer but only teaches generic material compositions for this structure. Thus, Su fails to teach “wherein the interposer comprises: a silicon substrate”.
Chen discloses wherein the interposer (Fig. 1A: device 104A. Note: electrical connections 130A/130B/136 interconnect the conductive features overlying and underlying the device, thus this structure performs the function of “an interposer”) comprises: a silicon substrate (124; [0037]: “silicon”). Modifying the modifying the material composition of “the interposer” so that it “comprises: a silicon substrate” would arrive at the claimed interposer configuration. A person of ordinary skill in the art would have had a reasonable expectation of success doing so because in each situation the interposer includes a semiconductor material composition (Su: [0018]: “semiconductor substrates”; Chen: [0037]: “semiconductor material, such as silicon”). Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date to try using a different material composition for the interposer. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense.” MPEP 2143 (1)(E).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Su.
Regarding claim 16, Su discloses the package of claim 15 (Fig. 12), but fails to teach “wherein the first integrated device and/or the second integrated device includes a plurality of through substrate vias”. However, Su teaches including a plurality of through substrate vias (42) with other devices (34). Modifying the second integrated device (device 58, citation repeated here) by including a plurality of substrate vias in the same way would arrive at the claimed vias configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation, the device is sandwiched between two metallization layers (device 34 is sandwiched between layers 92/94 and 50/52; device 58 is sandwiched between layers 50/52 and 68/70) and surrounded by post interconnects (device 34 is surrounded by posts 32; device 58 is surrounded by posts 56). Su provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the claimed “through substrate vias” configuration in that it would enhance interconnection density ([0036]: “This has the advantageous feature of increasing the total number of through-vias”) and enable reduced manufacturing cost ([0036]: “the cost that otherwise will be incurred for forming through-vias 32 is saved”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed “through substrate vias” configuration because it would enhance interconnection density and enable reduced manufacturing cost. MPEP 2143 (I)(G).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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