DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment/Restriction
Applicant’s election without traverse of Species I, Sub-Subspecies Sub A, and Claims 1-7, 14-15, and 18-23 in the reply filed on June 15, 2026 is acknowledged. However, Claim 18 reads on nonelected Fig. 9 as disclosed in [0145] of the Specification. Thus, Claims 8-13 and 16-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention. Election was made without traverse in the reply filed on June 15, 2026.
Specification
The title of the invention is broad and not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-7, 14-15, and 20-23 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2018/0254352 A1 to Koezuka et al. (“Koezuka”). As to claim 1, Koezuka discloses a display device, comprising: a substrate (705); a first gate electrode (120a) on the substrate (705); a first gate insulating film (114b, 116) on the first gate electrode (120a); an oxide semiconductor layer (108) on the first gate insulating film (114b, 116); a second gate insulating film (106) on the oxide semiconductor layer (108); a second gate electrode (104) on the second gate insulating film (106); a first interface layer (114a) between the first gate insulating film (114b, 116) and the oxide semiconductor layer (108); and a second interface layer (106a) between the second gate insulating film (106) and the oxide semiconductor layer (108), wherein the first interface layer (114a) and the second interface layer (106a) contain different amounts of oxygen from one another (See Fig. 1, Fig. 2, Fig. 6, Fig. 10, Fig. 13, Fig. 16, ¶ 0114, ¶ 0121, ¶ 0122, ¶ 0134, ¶ 0136, ¶ 0137, ¶ 0140, ¶ 0145, ¶ 0161, ¶ 0162, ¶ 0163, ¶ 0164, ¶ 0193, ¶ 0194, ¶ 0217, ¶ 0222, ¶ 0224, ¶ 0234, ¶ 0235, ¶ 0238, ¶ 0254, ¶ 0260, ¶ 0261, ¶ 0263, ¶ 0322, ¶ 0375, ¶ 0376, ¶ 0387), where the insulating layer 114b is provided with more excess oxygen than the insulating layer 114a by adding oxygen 130b into the insulating layer 114b. Further, oxygen 130a is also added to region 106a such that wherein the first interface layer and the second interface layer contain different amounts of oxygen from one another by the selective doping. As to claim 2, Koezuka further discloses wherein the first interface layer (114a) is an oxygen-insufficient area, and the second interface layer (106a) is an oxygen-excess area (See Fig. 2, ¶ 0140, ¶ 0260, ¶ 0322), where the oxygen-insufficient area is relative to the doped oxygen-excess area. As to claim 3, Koezuka further discloses wherein the first interface layer (114a) and the second interface layer (106a) contain silicon (Si), and wherein an amount of silicon of the first interface layer (114a) is larger than an amount of silicon of the second interface layer (106a) (See ¶ 0222, ¶ 0223, ¶ 0264) (Notes: the first interface layer of silicon oxide has more silicon relative to added oxygen-excess area of the second interface layer including aluminum nitride/oxide). As to claim 4, Koezuka further discloses wherein the amount of silicon of the first interface layer (114a) increases in a direction from a first interface adjacent to the oxide semiconductor layer (108) to a second interface adjacent to the first gate insulating film (114b, 116), and wherein the amount of silicon of the second interface layer decreases in a direction from a third interface adjacent to the second gate insulating film (106) to a fourth interface adjacent to the oxide semiconductor layer (108) (See Fig. 2, ¶ 0140, ¶ 0161). As to claim 5, Koezuka further discloses wherein a thickness of the first gate insulating film (114b, 116) is greater than a thickness of the second gate insulating film (106) (See Fig. 6, ¶ 0235, ¶ 0238, ¶ 0254), where the first gate insulating film is thicker than a sub-layer of the second gate insulating film. As to claim 6, Koezuka further discloses wherein the first gate insulating film (114b, 116) and the second gate insulating film (106) contain one or more of silicon oxide (SiOx), silicon oxynitride (SiON), or silicon nitride (SiNx) (See ¶ 0222, ¶ 0223, ¶ 0264). As to claim 7, Koezuka further discloses wherein the first gate insulating film (114b, 116) and the second gate insulating film (106) contain a same material (Si, O, N) (See ¶ 0222, ¶ 0223, ¶ 0264). As to claim 14, Koezuka further discloses wherein the oxide semiconductor (108) layer includes a channel region, and wherein the channel region, the first interface layer (114a) and the second interface layer (106a) overlap each other (See Fig. 6). As to claim 15, Koezuka discloses further comprising: a first conductor area (at 112a) positioned on a first side of the oxide semiconductor layer (108); a second conductor area (at 112b) positioned on a second side of the oxide semiconductor layer (108); a first electrode (112a) electrically connected to the first conductor area (at 112a); and a second electrode (112b) electrically connected to the second conductor area (at 112b) (See Fig. 6, ¶ 0114). As to claim 20, Koezuka further discloses wherein the first gate electrode (120a) includes a light shield material (See ¶ 0217) (Notes: the materials are met in [0126] of the Specification). As to claim 21, Koezuka discloses a display device, comprising: a substrate (705); a first gate electrode (120a) on the substrate (705); a first gate insulating film (114b, 116) on the first gate electrode (120a); an oxide semiconductor layer (108) on the first gate insulating film (114b, 116); a second gate insulating film (106) on the oxide semiconductor layer (108), the second gate insulating film (106) having a lesser thickness than the first gate insulating film (114b, 116); a second gate electrode (104) on the second gate insulating film (106); a first interface layer (114a) between the first gate insulating film (114b, 116) and the oxide semiconductor layer (108); and a second interface layer (106a) between the second gate insulating film (106) and the oxide semiconductor layer (108) (See Fig. 1, Fig. 2, Fig. 6, Fig. 10, Fig. 13, Fig. 16, ¶ 0114, ¶ 0121, ¶ 0122, ¶ 0134, ¶ 0136, ¶ 0137, ¶ 0140, ¶ 0145, ¶ 0161, ¶ 0162, ¶ 0163, ¶ 0164, ¶ 0193, ¶ 0194, ¶ 0217, ¶ 0222, ¶ 0224, ¶ 0234, ¶ 0235, ¶ 0238, ¶ 0254, ¶ 0260, ¶ 0261, ¶ 0263, ¶ 0322, ¶ 0375, ¶ 0376, ¶ 0387), where the first gate insulating film is thicker than a sub-layer of the second gate insulating film. As to claim 22, Koezuka further discloses wherein the first interface layer (114a) includes a first amount of silicon, the second interface layer (106a) includes a second amount of silicon, and the first amount is greater than the second amount (See ¶ 0222, ¶ 0223, ¶ 0264) (Notes: the first interface layer of silicon oxide has more silicon relative to added oxygen-excess area of the second interface layer including aluminum nitride/oxide). As to claim 23, Koezuka further discloses wherein the first interface layer (114a) includes a first amount of oxygen, the second interface layer (106a) includes a second amount of oxygen, and the first amount is smaller than the second amount (See Fig. 2, ¶ 0140, ¶ 0260, ¶ 0322), where the insulating layer 114b is provided with more excess oxygen than the insulating layer 114a by adding oxygen 130b into the insulating layer 114b. Further, oxygen 130a is also added to region 106a such that wherein the second interface layer contains more amount of oxygen by the additional doping.
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2018/0254352 A1 to Koezuka et al. (“Koezuka”) as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2014/0361290 A1 to Yamazaki et al. (“Yamazaki”). The teaching of Koezuka has been discussed above. As to claim 19, Koezuka does not further disclose wherein the first gate electrode and the second gate electrode are electrically connected to each other, Yamazaki does disclose wherein the first gate electrode (31) and the second gate electrode (13a) are electrically connected to each other (See Fig. 2, ¶ 0161) such that high on-state current and high field-effect mobility are obtained.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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/DAVID CHEN/Primary Examiner, Art Unit 2815
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