Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/14/2023 is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2014/0084357 A1) in view of Son et al. (KR 2021/0027771 A).
Regarding claim 1, Choi et al. teaches a semiconductor device (vertical cell-type semiconductor device 100a) comprising:
a gate stack structure (FIG. 4A, stack structure 100S) including interlayer insulating layers (interlayer insulating layer 104) and conductive layers (gate electrodes 134C), which are alternately stacked (FIG. 5O);
a channel structure (first vertical structure VS1) extending in a vertical direction (FIG. 5O) in the gate stack structure (stack structure 100S); and
memory structures (combination of barrier layer 114, charge trap layer 116, and tunneling layer 118) interposed between the conductive layers (gate electrodes 134C) and the channel structure (first vertical structure VS1),
wherein each of the memory structures (combination of barrier layer 114, charge trap layer 116, and tunneling layer 118) includes a blocking insulating layer (barrier layer 114) and a charge trap layer (charge trap layer 116), which are sequentially formed (FIG. 5O) on a sidewall of each of the conductive layers (gate electrodes 134C), and
wherein sidewalls of the interlayer insulating layers (interlayer insulating layer 104), which are in contact with the channel structure (first vertical structure VS1), are located on the same line (FIG. 5O, sidewalls of 104 intersect vertically with sidewalls of 116) as a sidewall of the charge trap layer (charge trap layer 116), which is in contact with the channel structure (first vertical structure VS1).
Choi et al. is silent to side portions of the interlayer insulating layers, which are in contact with the channel structure, further protrude toward the channel structure as compared with the sidewall of the charge trap layer.
However, Son et al. teaches side portions of the interlayer insulating layers (second insulating pattern 425), which are in contact with the channel structure (channel 270), further protrude (FIG. 27) toward the channel structure as compared with the sidewall of the charge trap layer (charge trapping pattern 245).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have modified the interlayer insulating layers of Choi et al. to have extended further than the charge trap layers toward the vertical channel as recited in Son et al., which teaches a tapered vertical channel with protruding interlayer insulating layers. Narrowing the channel downward increases gate to channel coupling ratio and thus leads to stronger threshold voltage and lower leakage current when device is off. When power supply is interrupted, the device draws less current from leakage voltage, reducing power loss.
Regarding claim 2, Choi et al. in view of Son et al. teaches the semiconductor device of claim 1. Choi et al. teaches wherein the blocking insulating layer (barrier layer 114) and the charge trap layer (charge trap layer 116) are interposed in a space between (FIG. 5O) the interlayer insulating layers (interlayer insulating layer 104).
Choi is silent to wherein the interlayer insulating layers further protrude toward the channel structure as compared with the conductive layers.
However, Son et al. teaches wherein the interlayer insulating layers (second insulating pattern 425) further protrude (FIG. 27) toward the channel structure (channel 270) as compared with the conductive layers (gate electrode 460).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have modified the interlayer insulating layers of Choi et al. to have extended further than the conductive layers toward the vertical channel as recited in Son et al., which teaches a tapered vertical channel with protruding interlayer insulating layers. A tapered vertical channel with interlayer insulating layers extending further than the conductive layers toward the channel has tighter gate control toward the bottom cells and is thus less sensitive to power supply loss. Stored state remains readable for longer when power supply is interrupted, thus improving data retention.
Regarding claim 3, Choi et al. in view of Son et al. teaches the semiconductor device of claim 1. Son et al. teaches wherein the charge trap layers (charge trapping pattern 245) formed on the sidewalls of the respective conductive layers (third gate electrode 476) are spaced apart ([0121] and FIG. 21) from each other.
It would have been obvious to one of ordinary skill in the art before the effective filing date to have modified the charge trap layers in Choi et al. that run continuously down vertically to instead have them spaced apart, as taught in Son et al. Discrete charge trap layers interrupt path of conduction, isolating charge from migrating laterally. Segmenting the charge trap layers into electrically separated sections (as opposed to forming continuous) reduces capacitive coupling area, requiring less energy to drive word lines and less voltage drag in between, thus allowing faster settling time.
Regarding claim 4, Choi et al. in view of Son et al. teaches the semiconductor device of claim 1. Choi et al. teaches wherein heights of upper surfaces (abutting lower surface of layer 126 in FIG. 5O) of the blocking insulating layer (barrier layer 114) and the charge trap layer (116), which correspond to any one of the conductive layers (gate electrodes 134C), substantially are the same (FIG. 5O).
Regarding claim 5, Choi et al. in view of Son et al. teaches the semiconductor device of claim 1. Choi et al. teaches wherein heights of lower surfaces (abutting upper surface of layer 102) of the blocking insulating layer (barrier layer 114) and the charge trap layer (116), which correspond to any one of the conductive layers (gate electrodes 134C), are substantially the same (FIG. 5O).
Regarding claim 6, Choi et al. in view of Son et al. teaches the semiconductor device of claim 1. Choi et al. teaches the semiconductor device of claim 1, wherein the channel structure (first vertical structure VS1) includes:
a tunnel insulating layer (tunneling layer 118) extending in a vertical direction (FIG. 5O) along the sidewalls of the interlayer insulating layers (interlayer insulating layer 104) and the sidewalls of the charge trap layer (charge trap layer 116); and
a channel layer (channel pattern 120) extending in the vertical direction (FIG. 5O) along a sidewall of the tunnel insulating layer (tunneling layer 118).
Regarding claim 7, Choi et al. teaches a semiconductor device comprising:
a gate stack structure (FIG. 4A, stack structure 100S) including interlayer insulating layers (interlayer insulating layer 104) and conductive layers (gate electrodes 134C), which are alternately stacked (FIG. 5O);
a channel layer (channel pattern 120) extending in a vertical direction (FIG. 5O) in the gate stack structure (FIG. 4A, stack structure 100S); and
memory structures (combination of barrier layer 114, charge trap layer 116, and tunneling layer 118) interposed between the conductive layers (gate electrodes 134C) and the channel structure (first vertical structure VS1),
wherein each of the memory structures (combination of barrier layer 114, charge trap layer 116, and tunneling layer 118) includes a blocking insulating layer (barrier layer 114), a charge trap layer (charge trap layer 116), and a tunnel insulating layer (tunneling layer 118), which are sequentially formed (FIG. 5O) on a sidewall of each of the conductive layers (gate electrodes 134C), and
wherein sidewalls of the interlayer insulating layers (interlayer insulating layer 104), which are in contact with the channel structure (first vertical structure VS1), are located on the same line (FIG. 5O, sidewalls of 104 intersect vertically with sidewalls of 116) as a sidewall of the tunnel insulating layer (tunneling layer 118), which is in contact with the channel structure (first vertical structure VS1).
Choi et al. does not recite side portions of the interlayer insulating layers, which are in contact with the channel structure, further protrude toward the channel structure as compared with the sidewall of the tunnel insulating layer.
However, Son et al. teaches side portions of the interlayer insulating layers (second insulating pattern 425), which are in contact with the channel structure (channel 270), further protrude (FIG. 27) toward the channel structure as compared with the sidewall of the tunnel insulating layer (250).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have modified the interlayer insulating layers of Choi et al. to have extended further than the tunnel insulating layers toward the vertical channel as recited in Son et al., which teaches a tapered vertical channel with protruding interlayer insulating layers. Narrowing the channel downward increases gate to channel coupling ratio and thus leads to stronger threshold voltage and lower leakage current when device is off. When power supply is interrupted, the device draws less current from leakage voltage, reducing power loss.
Regarding claim 8, Choi et al. in view of Son et al. teaches the semiconductor device of claim 7. Choi et al. teaches wherein the blocking insulating layer (barrier layer 114), the charge trap layer (charge trap layer 116), and the tunnel insulating layer (tunneling layer 118) are interposed in a space between (FIG. 5O) the interlayer insulating layers (interlayer insulating layer 104).
Choi is silent to wherein the interlayer insulating layers further protrude toward the channel structure as compared with the conductive layers.
However, Son et al. teaches wherein the interlayer insulating layers (second insulating pattern 425) further protrude (FIG. 27) toward the channel structure (channel 270) as compared with the conductive layers (gate electrode 460).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have modified the interlayer insulating layers of Choi et al. to have extended further than the conductive layers toward the vertical channel as recited in Son et al., which teaches a tapered vertical channel with protruding interlayer insulating layers. A tapered vertical channel with interlayer insulating layers extending further than the conductive layers toward the channel has tighter gate control toward the bottom cells and is thus less sensitive to power supply loss. Stored state remains readable for longer when power supply is interrupted, thus improving data retention.
Regarding claim 9, Choi et al. in view of Son et al. teaches the semiconductor device of claim 7. Son et al. teaches wherein the charge trap layers (charge trapping pattern 245) formed on the sidewalls of the respective conductive layers (third gate electrode 476) are spaced apart ([0121] and FIG. 21) from each other.
It would have been obvious to one of ordinary skill in the art before the effective filing date to have modified the charge trap layers in Choi et al. that run continuously down vertically to instead have them spaced apart, as taught in Son et al. Discrete charge trap layers interrupt path of conduction, isolating charge from migrating laterally. Segmenting the charge trap layers into electrically separated sections (as opposed to forming continuous) reduces capacitive coupling area, requiring less energy to drive word lines and less voltage drag in between, thus allowing faster settling time.
Regarding claim 10, Choi et al. in view of Son et al. teaches the semiconductor device of claim 7. Choi et al. teaches wherein heights of upper surfaces (abutting lower surface of layer 126 in FIG. 5O) of the blocking insulating layer (barrier layer 114), the charge trap layer (116), and the tunnel insulating layer (tunneling layer 118), which correspond to any one of the conductive layers (gate electrodes 134C), are substantially the same (FIG. 5O).
Regarding claim 11, Choi et al. in view of Son et al. teaches the semiconductor device of claim 7. Choi et al. teaches wherein heights of lower surfaces (abutting upper surface of layer 102) of the blocking insulating layer (barrier layer 114), the charge trap layer (116), and the tunnel insulating layer (tunneling layer 118), which correspond to any one of the conductive layers (gate electrodes 134C), are substantially the same (FIG. 5O).
Conclusion
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/JEANNE MYON KIM/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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