Prosecution Insights
Last updated: October 25, 2026
Application No. 18/540,625

AVALANCHE PHOTODIODE

Non-Final OA §102§112
Filed
Dec 14, 2023
Priority
Dec 20, 2022 — FR 2214005
Examiner
PATERSON, BRIGITTE A
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
STMicroelectronics N.V.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
300 granted / 391 resolved
+8.7% vs TC avg
Strong +22% interview lift
Without
With
+22.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
25 currently pending
Career history
416
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
46.7%
+6.7% vs TC avg
§102
26.9%
-13.1% vs TC avg
§112
23.7%
-16.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 391 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 16-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected method, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 8/11/2026. Applicant's election with traverse of group I in the reply filed on 8/11/2026 is acknowledged. The traversal is on the ground(s) that the method has been amended to remove the one-way distinctiveness between the device and method. As such claim 15 is now considered a linking claim between the elected device of Group I and the method of Group II. However, the dependent claims of the method are not generic to both the method and device and remain withdrawn The requirement is still deemed proper and is therefore made FINAL. Claim Objections Claims 1, 2, 4, 9, 10, 11 are objected to because of the following informalities: claims 1, 2, 4, 9, 10, and 11 recite “first region” however this lacks antecedent basis as the nomenclature used to introduce the claim term is “first epitaxial semiconductor region” and the claims should consistently use the same terminology when referring back to this feature. Appropriate correction is required. Claim 4 is objected to because of the following informalities: claim 4 recites “third region” however this lacks antecedent basis as the nomenclature used to introduce the claim term is “third semiconductor region” and the claims should consistently use the same terminology when referring back to this feature. Appropriate correction is required. Claims 7 and 8 are objected to because of the following informalities: claims 7 and 8 recite “second region” however this lacks antecedent basis as the nomenclature used to introduce the claim term is “second semiconductor region” and the claims should consistently use the same terminology when referring back to this feature. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 2-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 2 and 3 recite multiple instances of “heavily doped”. The term "heavily" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “Heavily” is defined as " to a great degree” (see Merriam Webster online dictionary). This language is indefinite as the specification does not describe what the minimum dopant concentration of the regions must be in order to be considered heavily doped. Thus, it is unclear because there is no disclosed or claimed minimum doping threshold above which one can unambiguously define a silicon layer as being “heavily” doped. If one were to poll 100 people having ordinary skill in the art, there would be many different responses for the boundaries. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Therefore, each claim and all claims depending therefrom is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claims 2-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 2 recites “substantially parallel”. The term "substantially" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “Substantially” is defined as "being largely but not wholly that which is specified” (see Merriam Webster online dictionary). This language is indefinite as the specification does not describe what is required of the planes in order to be considered “substantially parallel”. The term “substantially” modifies a target, and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “substantially” the target any more. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, or some other percentage) or within a certain number of units of the target and specifically which of these possible values defines the boundaries. In geometry, a set of planes in space are parallel if the planes do not intersect. For a set of planes to be substantially parallel there would exist some deviation from this geometric requirement however Applicant has not defined the metes and bounds of this deviation. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Furthermore, there is no objective consensus in the art of the boundaries for substantially parallel. US 2019/0237515 Jung [0019] (+/- 5, +/- 10, +/- 15 degrees from the target) “In this specification, when the term such as vertical, horizontal, orthogonal or parallel is used while defining an angle, it means substantially vertical, horizontal, orthogonal, or parallel to the extent that the desired effect is not impaired, which includes, for example, an error that takes a production error or a deviation (variation), and the like, into account. For example, each case of the foregoing may include an error within about ±15 degrees, an error within about ±10 degrees or an error within about ±5 degrees” US 2017/0234569 A1 Emmos [0103] (+/- 10 degrees from geometric parallel) “In this, substantially parallel may be defined as being within about plus or minus 10 degrees from a geometric parallel.” US 9412674 Kim Col. 7 lines 1-3 (within a defined or specified tolerance) “Substantially” parallel means that the referenced wires are parallel within a defined or specified tolerance.” US 2019/0165237 Hertzberg [0080] (tolerance defined by this or similar aspect ratio) “Essentially, walls 602A and 602B of trench 602 are substantially parallel within a tolerance defined by this or similar aspect ratio.” PNG media_image1.png 422 468 media_image1.png Greyscale US 2011/0162712 Tillin [0063] (+/- 20 degrees) “As used herein, "substantially parallel" is defined as two faces or planes having an angle less than 20.degree. and, more preferably, less than 10.degree. relative to each other.” Therefore, the claims are rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 9 recites “substantially constant fashion”. The term "substantially" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “Substantially” is defined as "being largely but not wholly that which is specified” (see Merriam Webster online dictionary). This language is indefinite as the specification does not describe what is required of the doping profile in order to be considered “doped in a substantially constant fashion”. The term “substantially” modifies a target, and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “substantially” the target any more. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, or some other percentage) or within a certain number of units of the target and specifically which of these possible values defines the boundaries. In geometry, a set of planes in space are parallel if the planes do not intersect. For a set of planes to be substantially parallel there would exist some deviation from this geometric requirement however Applicant has not defined the metes and bounds of this deviation. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Therefore, the claim is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-9, 11-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2011/0241149 A1 (Mazzillo). Re claim 1, Mazzillo teaches an avalanche photodiode (photodiode 1), comprising: a main PN junction (junction between P+ strip regions 14 and N type enriched region 20) adapted to being reverse-biased (conventional operation of a photodiode [0006-0009]); and a plurality of semiconductor regions including at least: a first epitaxial semiconductor region (P- guard ring 24) of a first conductivity type; a second semiconductor region (N- type second epitaxial layer 6) of a second conductivity type, the second region being arranged to at least partially surround the first region, and comprising surfaces in contact with surfaces of the first region (Fig. 2); and a third semiconductor region (P++ regions 18) (Fig. 2). PNG media_image2.png 434 660 media_image2.png Greyscale Re claim 2, Mazzillo teaches, wherein: the main PN junction is formed by fourth (P+ strip regions 14) and fifth regions (N type enriched region 20) of the plurality of semiconductor regions; the fourth region being heavily doped with the first conductivity type (p+ strip regions 14), for example more heavily doped than the first region (p+ regions more heavily doped than p- region), and being formed from a first surface of the photodiode (top surface); and the fifth region being heavily doped with the second conductivity type (N type enriched region), and being formed under, and in contact with, the fourth region (Fig. 2); the fourth and fifth regions being located at the center of the photodiode in a plane substantially parallel to the first surface (Fig. 2). Re claim 3, Mazzillo teaches wherein a sixth region (N+ sinker region 26) of the plurality of semiconductor regions is laterally formed around, and at a distance from, the fourth region from the first surface of the photodiode, the sixth region being heavily doped with the second conductivity type (n+ region). Re claim 4, Mazzillo teaches wherein the third semiconductor region (P++ regions 18 Fig. 2) of the plurality of semiconductor regions is formed between the first surface of the photodiode and the first region, the third region being an epitaxial region of the first conductivity type, and the fourth, fifth, and sixth regions being formed by doping. Re claim 5, Mazzillo teaches wherein a guard ring region (guard ring 24) of the plurality of semiconductor regions is formed around the fourth region, the guard ring region being of the first conductivity type and being more lightly doped than the fourth region (p- region Fig. 2). Re claim 6, Mazzillo teaches wherein the semiconductor regions are formed in a well (first epitaxial layer 4) delimited by a deep trench insulation (lateral insulation region 30) extending in a direction perpendicular to the first surface of the photodiode (Fig. 2). Re claim 7, Mazzillo teaches wherein the second region (N- type second epitaxial layer 6) comprises a lateral portion located between the first region and the deep trench insulation (Fig. 2). Re claim 8, Mazzillo teaches wherein the second region comprises a buried portion (N- type second epitaxial layer 6 under portions 24) located between the first region and a second surface of the photodiode (bottom surface of the photodiode) opposite to the first surface (Fig. 2). Re claim 9, Mazzillo teaches wherein the first region is doped in substantially constant fashion in a direction perpendicular to the first surface of the photodiode (there is no discussion that region 6 has any gradient therefore it is understood the doped regions having substantially constant dopant profiles in the z direction). Re claim 11, Mazzillo teaches wherein the first region comprises a first portion and a second portion narrower, in a plane parallel to the first surface, than the first portion, and located between the first portion and the main PN junction (middle portion of region 6 is narrower under the region 20). Re claim 12, Mazzillo teaches wherein the first region surrounds the main PN junction, including a first portion located under the main PN junction, and a second portion extending all the way to the first surface of the photodiode (Fig. 2). Re claim 13, Mazzillo teaches wherein the first region is inside of the second region (Fig. 2). Re claim 14, Mazzillo teaches wherein each dimension of the photodiode, in a plane parallel to a first surface of the photodiode, is smaller than 6 μm and/or the height of the photodiode is in the range from 3 to 15 μm (thickness of h4 is between 8-12 microns and thickness h6 is between 3-5 microns therefore the total thickness of the photodiode is between 11-17 microns [0037]). Re claim 15, Mazzillo teaches a method, comprising: manufacturing an avalanche photodiode (photodiode 1) a main PN junction (junction between P+ strip regions 14 and N type enriched region 20) adapted to being reverse-biased (conventional operation of a photodiode [0006-0009]), the method including: forming of a plurality of semiconductor regions including at least: forming of a first epitaxial semiconductor region (P- guard ring 24) of a first conductivity type; forming of a second semiconductor region (N- type second epitaxial layer 6) of a second conductivity type, the second region being arranged to at least partially surround the first region, and comprising surfaces in contact with surfaces of the first region (Fig. 2); and forming of a third semiconductor region (P++ regions 18) (Fig. 2). PNG media_image2.png 434 660 media_image2.png Greyscale Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. BRIGITTE A. PATERSON Primary Examiner Art Unit 2896 /BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896
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Prosecution Timeline

Dec 14, 2023
Application Filed
Oct 02, 2026
Non-Final Rejection mailed — §102, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
99%
With Interview (+22.4%)
2y 8m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 391 resolved cases by this examiner. Grant probability derived from career allowance rate.

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