Prosecution Insights
Last updated: October 02, 2026
Application No. 18/540,847

LOW-VARIABILITY, HIGH-DENSITY DISC CELL WITH HORIZONTALLY ALIGNED ELECTRODES

Non-Final OA §102
Filed
Dec 14, 2023
Examiner
PATERSON, BRIGITTE A
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
297 granted / 388 resolved
+8.5% vs TC avg
Strong +23% interview lift
Without
With
+22.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
21 currently pending
Career history
411
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
46.6%
+6.6% vs TC avg
§102
27.0%
-13.0% vs TC avg
§112
23.6%
-16.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 388 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 3-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2023/0240160 A1 (Allegra). Re claim 1, Allegra teaches a memory device, comprising: a dielectric substrate (insulating layer 111); a first metal electrode contact layer (bottom contact 112) coupled to the dielectric substrate; a metal heater element (heater 102) disposed longitudinally on top of the first metal electrode contact layer; a first section of a layer of crystalline phase change material (narrow bottom portion of memory region 106) positioned perpendicular to and in contact with an exposed first end of the longitudinally disposed metal heater element (Fig. 11C); a first section of a second metal electrode contact layer (electrode 108) positioned parallel to and spaced from, the first section of the layer of crystalline phase change material; and a dielectric spacer (insulating layer 104) positioned between the layer of crystalline phase change material and the first section of the second metal electrode contact layer (Fig. 11C). PNG media_image1.png 477 698 media_image1.png Greyscale Re claim 3, Allegra teaches further comprising: a second section (top portion of 106 in contact with 108) of the layer of crystalline phase change material positioned parallel to the metal heater element; and a second section of the second metal electrode contact layer positioned parallel to the metal heater element and on top of the second section of the layer of crystalline phase change material (Fig. 11C). Re claim 4, Allegra teaches further comprising a contact (conductive vias [0054]) positioned on top of the second section of the second metal electrode contact layer. Re claim 5, Allegra teaches further comprising: a third section of the layer of crystalline phase change material (right portion of 106 in contact with the top horizontal portion of 102) positioned perpendicular to and in contact with an exposed second end of the longitudinally disposed metal heater element; and a third section of the second metal electrode contact layer positioned parallel to and spaced from, the third section of the layer of crystalline phase change material (Fig. 11C). Re claim 6, Allegra teaches further comprising a contact positioned on top of the second section of the second metal electrode contact layer (conductive vias [0054]). Claim(s) 9, 11-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0181546 A1 (Ok). Re claim 9, Ok teaches a memory device, comprising: a dielectric substrate (first dielectric layer 106); a first metal electrode contact layer (bottom electrodes 110) coupled to the dielectric substrate; a metal heater element (heater 116) extending linearly across and on top of a top surface of the first metal electrode contact (Fig. 7); a second metal contact electrode (top electrode contacts 136) positioned above the metal heater element and above the first metal electrode contact (Fig. 7); a layer of crystalline phase change material (phase change material layer 126) positioned parallel to a side wall of the first metal electrode contact (sidewalls of 110 and 126 are parallel) and perpendicular to a first end of the metal heater element; and an electrode layer (via contact 138/second metal layer 142) coupled to the second metal contact electrode and positioned parallel to the layer of crystalline phase change material and perpendicular to the first end of the heater element (Fig. 7). PNG media_image2.png 508 682 media_image2.png Greyscale Re claim 11, Ok teaches further comprising a section of insulation (third dielectric layer 132) positioned between the heater element and the second metal contact electrode, wherein the layer of crystalline phase change material extends around the section of insulation, over a span of the heater element, and under the second metal contact electrode (Fig. 7). Re claim 12, Ok teaches wherein the layer of crystalline phase change material extends down a side wall of the section of insulation in contact with a second end of the metal heater element (Fig. 7). Allowable Subject Matter Claims 2, 10, 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. BRIGITTE A. PATERSON Primary Examiner Art Unit 2896 /BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Dec 14, 2023
Application Filed
Sep 22, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
99%
With Interview (+22.6%)
2y 8m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 388 resolved cases by this examiner. Grant probability derived from career allowance rate.

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