Prosecution Insights
Last updated: July 17, 2026
Application No. 18/540,971

INTEGRATED CIRCUIT DEVICE INCLUDING DIES ARRANGED FACE-TO-FACE

Non-Final OA §102
Filed
Dec 15, 2023
Priority
Aug 08, 2023 — provisional 63/531,385
Examiner
PAGE, STEVEN MITCHELL CHR
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Microchip Technology Incorporated
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
378 granted / 454 resolved
+15.3% vs TC avg
Moderate +9% lift
Without
With
+9.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
16 currently pending
Career history
472
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
63.7%
+23.7% vs TC avg
§102
25.8%
-14.2% vs TC avg
§112
6.6%
-33.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 454 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-13, 15, and 21-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kelkar et al. (US 6084308 A, hereinafter Kelkar) With regards to claim 1, Kelkar discloses a method, (FIGS. 3A-3D) comprising: forming an integrated circuit (IC) device, wherein forming the IC device includes: forming a first die block including: a first die block substrate (substrate 302) comprising a mold compound;(die attach material 308) a first die (first die 306) at least partially embedded in the first die block substrate; (See FIG. 3A) a plurality of first die contacts (I/O pads 312) located in a lateral footprint of the first die; and a plurality of first die block contacts (conductive landings 314) located laterally outside the lateral footprint of the first die; arranging a second die (second die 316) in a face-to-face orientation relative to the first die, wherein a lateral footprint of the second die is larger than a lateral footprint of the first die, (See FIG. 3B, showing the larger footprint) and wherein the second die includes (a) a plurality of second die inner contacts (contacts 320) and (b) a plurality of second die outer contacts; (contacts 318) spatially aligning the second die relative to the first die block; and performing a bonding process to bond the second die to the first die block, wherein the bonding process includes (a) bonding respective second die inner contacts to respective first die contacts to define a plurality of inner electrical connections between the second die and the first die and (b) bonding respective second die outer contacts to respective first die block contacts to define a plurality of outer electrical connections outside the lateral footprint of the first die. (see FIG. 3B, showing the bonding and alignment between contacts 312/314 and contacts 318/320) With regards to claim 2, Kelkar discloses the method of Claim 1, wherein the first die block includes a laterally extending conductor (contact bumps 304) formed over the first die block substrate, the laterally extending conductor connected to a respective one of the plurality of first die block contacts and extending laterally outside the lateral footprint of the second die; wherein the laterally extending conductor comprises a bond pad for bonding the IC device to another IC device. (see FIG. 3B, showing the extension outside the die 316 and for bonding one IC to another) With regards to claim 3, Kelkar discloses the method of Claim 2, wherein the respective first die block contact is bonded to a respective one the second die outer contacts to define an electrical connection between the laterally extending conductor and the second die. (See FIG. 3B, showing the bonding) With regards to claim 4, Kelkar discloses the method of Claim 1, wherein the first die block includes a plurality of laterally extending conductors, (pads 304) wherein respective laterally extending conductors define electrical connections between the first die and respective ones of the plurality of first die block contacts located laterally outside the lateral footprint of the first die. (see FIG. 3B) With regards to claim 5, Kelkar discloses the method of Claim 1, wherein: the plurality of first die contacts comprise a first plurality of pillars (left most pads 304) extending upwardly from a first side of the first die; and the plurality of first die block contacts comprise a second plurality of pillars (right most pads 304) extending upwardly from the first die block substrate. (See FIG. 3B) With regards to claim 6, Kelkar discloses the method of Claim 1, wherein after spatially aligning the second die relative to the first die block, the plurality of first die contacts and the plurality of first die block contacts are located in the lateral footprint of the second die. (See FIG. 3B) With regards to claim 7, Kelkar discloses the method of Claim 1, wherein: one or more first die block contacts of the plurality of first die block contacts define one or more first alignment contacts; one or more second die outer contacts of the plurality of second die outer contacts define one or more second alignment contacts; and spatially aligning the second die relative to the first die block comprises aligning the one or more second alignment contacts with the one or more first alignment contacts; and the method comprises bonding respective second alignment contacts to respective first alignment contacts. (see FIG. 3B, where the contacts are aligned as shown) With regards to claim 8, Kelkar discloses the method of Claim 7, wherein a respective diameter of a respective first alignment contact of the one or more first alignment contacts is larger than a respective diameter of a respective first die contact of the plurality of first die contacts. (See FIG. 3B) With regards to claim 9, Kelkar discloses the method of Claim 7, wherein a respective diameter of a respective second alignment contact of the one or more second alignment contacts is larger than a respective diameter of a respective second die outer contact of the plurality of second die outer contacts. (See FIG. 3B) With regards to claim 10, Kelkar discloses the method of Claim 1, wherein the first die comprises a digital die, and the second die comprises an analog die. (analog to digital, see at least description of prior art) With regards to claim 11, Kelkar discloses the method of Claim 1, comprising providing a flux between the first die and the second die prior to performing the bonding process, and wherein the bonding process comprises a mass reflow process. (“After the second die 316 is positioned over the first die 306 in operation 206, a reflow process is implemented in operation 208.”) With regards to claim 12, Kelkar discloses the method of Claim 1, comprising forming the plurality of first die contacts and the plurality of first die block contacts concurrently. (See FIG. 3B) With regards to claim 13, Kelkar discloses the method of Claim 1, wherein: forming the first die block includes forming at least one vertically-extending alignment guide; and spatially aligning the second die relative to the first die block comprises using the at least one vertically-extending alignment guide to physically constrain a spatial alignment of the second die relative to the first die block. (See FIG. 3B) With regards to claim 15, Kelkar discloses the method of Claim 1, comprising mounting the IC device in a quad flat no-leads (QFN) package. (See FIG. 3B, showing the no leads structure) With regards to claim 21, Kelkar discloses a method, (FIGS. 3A-3D) comprising: forming an integrated circuit (IC) device, wherein forming the IC device includes: forming a first die block including: a first die block substrate (substrate 302) comprising a mold compound;(die attach material 308) a first die (first die 306) at least partially embedded in the first die block substrate; (See FIG. 3A) a plurality of first die contacts (I/O pads 312) located in a lateral footprint of the first die; and a plurality of first alignment contacts (conductive landings 314) located laterally outside the lateral footprint of the first die; arranging a second die (second die 306) in a face-to-face orientation relative to the first die, wherein a lateral footprint of the second die is larger than a lateral footprint of the first die, and wherein the second die includes (a) a plurality of second die inner contacts (contacts 320) and (b) a plurality of second die outer contacts; (contacts 318) spatially aligning the second die relative to the first die block, including aligning the one or more second alignment contacts with the one or more first alignment contacts; (see FIG. 3B) and performing a bonding process to bond the second die to the first die block, wherein the bonding process includes (a) bonding respective second die inner contacts to respective first die contacts to define a plurality of inner electrical connections between the second die and the first die and (b) bonding respective second alignment contacts provided on the second die with respective first alignment contacts provided on the first die block. (see FIG. 3B, showing the bonding and alignment between contacts 312/314 and contacts 318/320) With regards to claim 22, Kelkar discloses the method of Claim 21, wherein a respective diameter of a respective first alignment contact of the one or more first alignment contacts is larger than a respective diameter of a respective first die contact of the plurality of first die contacts. (See FIG. 3B, showing the larger diameter) With regards to claim 23, Kelkar discloses the method of Claim 21, wherein a respective diameter of a respective second alignment contact of the one or more second alignment contacts is larger than a respective diameter of a respective second die inner contact of the plurality of second die inner contacts. (See FIG. 3B, showing the larger diameter) With regards to claim 24, Kelkar discloses the method of Claim 21, wherein the first die block includes a laterally extending conductor (bumps 304) formed over the first die block substrate, the laterally extending conductor connected to a respective one of the plurality of first alignment contacts and extending laterally outside the lateral footprint of the second die; wherein the laterally extending conductor comprises a bond pad for bonding the IC device to another IC device. . (see FIG. 3B, showing the extension outside the die 316 and for bonding one IC to another) With regards to claim 25, Kelkar discloses the method of Claim 21, wherein the first die block includes a plurality of laterally extending conductors, (bumps 304) wherein respective laterally extending conductors define electrical connections between the first die and respective ones of the plurality of first alignment contacts located laterally outside the lateral footprint of the first die. . (see FIG. 3B, showing the extension outside the die 316 and for bonding one IC to another) Allowable Subject Matter Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: None of the cited references teach or suggest, either alone or in combination, at least “forming a panel-level structure, including: arranging a plurality of first dies, including the first die, on a panel-level carrier; and overmolding the plurality of first dies to form a panel-level substrate with the plurality of first dies embedded in the panel-level substrate; wherein a respective portion of the panel-level substrate defines the first die block substrate, and wherein the first die block includes the first die block substrate having the first die embedded therein; and after aligning and bonding the second die to the first die block, performing a singulation process to singulate the first die block having the first die embedded therein and the second die mounted thereto,” as recited in claim 14. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Trimberger (US 10665579 B2) – bonding of two die devices Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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Prosecution Timeline

Dec 15, 2023
Application Filed
Apr 07, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
92%
With Interview (+9.0%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 454 resolved cases by this examiner. Grant probability derived from career allowance rate.

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