Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Objections to the Specification
The disclosure is objected to because of the following informality:
In paragraph 22, it reads in part “PN junction 130 is oriented along an axis that intersects surface 130, where the P-type doped region 124 can be configured as a multiplication region.” This is objected to because 130 has already been identified as the PN junction. Paragraph 22 references Fig. 1. Fig. 1 shows PN junction 130 intersecting surface 103.
Appropriate correction is required.
Claim Rejections 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 9, 10, 11, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a second PN junction in the semiconductor substrate, the PN junction including one of the N-type or P-type doped regions and oriented along a second axis that intersects the surface.” It is indefinite because it is unclear if “the PN junction” being referred to is the first or second PN junction. For purposes of examination it is being interpreted as “a second PN junction in the semiconductor substrate, the second PN junction including one of the N-type or P-type doped regions and oriented along a second axis that intersects the surface.”
Claim 9 recites "at least a portion of the dielectric layer is transparent" in line 1. There is insufficient antecedent basis for this limitation in the claim. The dielectric layer appears in claim 8. For purposes of examination the claim is being interpreted as depending from claim 8.
Claim 10 recites “the second P-type doped region being part of the PN junction.” It is indefinite because it is unclear if “the PN junction” being referred to is the first or second PN junction. For purposes of examination it is being interpreted as “the second P-type doped region being part of the second PN junction.”
Claim 11 recites "an optically-opaque layer over a portion of the dielectric layer containing the first and second field plates" in line 1. There is insufficient antecedent basis for this limitation in the claim. The dielectric layer appears in claim 8. For purposes of examination the claim is being interpreted as depending from claim 8.
Claim 19 recites the limitation " and the avalanche photodiode further comprises a second P-type doped region under the portion of the dielectric layer" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. The dielectric layer is never given any portions in claim 18. The claim is further indefinite because it does not describe what portion of the dielectric layer is claimed. For purposes of examination the claim is being interpreted as reading “and the avalanche photodiode further comprises a second P-type doped region under a portion of the dielectric layer.”
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 2 rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 2 reads “The semiconductor device of claim 1, wherein the first field plate is electrically coupled to the first terminal, and the second field plate is electrically coupled to the second terminal.” However, claim 1 already contains “the first field plate electrically coupled to the first terminal and extending over a first part of the semiconductor substrate between the N-type and P-type doped regions; and a second field plate on the surface, the second field plate electrically coupled to the second terminal and extending over a second part of the semiconductor substrate between the N-type and P-type doped region, the first and second field plates being separated by a gap.” . Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 6, 7, 13-15 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hezar et. al. (US 20220352406), hereinafter referred to as Hezar.
Regarding claim 1, Hezar teaches a semiconductor device comprising: a semiconductor substrate having a surface (Hezar, Fig. 7, 120) ; an N-type doped region in the semiconductor substrate (Hezar, Fig. 7, 140, para. 25); a P-type doped region in the semiconductor substrate (Hezar, Fig 7, 120 para. 18), the P-type doped region and the N-type doped region forms a first PN junction oriented along a first axis parallel to the surface (Hezar, Fig 7, Junction 135, 140, 145, Para 13); a second PN junction in the semiconductor substrate, the PN junction including one of the N-type or P-type doped regions and oriented along a second axis that intersects the surface (Hezar, Fig 7, Junction 135, 140, 145, Para 13); a first terminal (175) electrically coupled to the N-type doped region (Hezar, Fig 7); a second terminal (171) electrically coupled to the P-type doped region (Hezar, Fig 7); a first field plate (182) on the surface, the first field plate electrically coupled to the first terminal (par 29) and extending over a first part of the semiconductor substrate between the N-type and P-type doped regions (Hezar, Fig 7); and a second field plate (181) on the surface, the second field plate electrically coupled to the second terminal (par 29) and extending over a second part of the semiconductor substrate between the N-type and P-type doped region (Hezar, Fig 7), the first and second field plates being separated by a gap (Hezar ,Fig 7).
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Regarding claim 2, Hezar teaches the semiconductor device of claim 1, wherein the first field plate is electrically coupled to the first terminal (Hezar, para. 29), and the second field plate is electrically coupled to the second terminal (Hezar, para. 29).
Regarding claim 4, Hezar teaches the semiconductor device of claim 1, wherein the first and second field plates comprise polycrystalline silicon (Hezar, para. 29). NOTE: Hezar refers to the material as polysilicon, which a person having ordinary skill in the art before the filing date of the invention would recognize as a term for polycrystalline silicon.
Regarding claim 6, Hezar teaches the semiconductor device of claim 1, wherein the second PN junction is part of an avalanche photodiode (Hezar, paras 26-28).
Regarding claim 7, Hezar teaches the semiconductor device of claim 6, wherein the first terminal is a cathode of the avalanche photodiode (Hezar, para. 23, 29), and the second terminal is an anode of the avalanche photodiode (Hezar, para. 23).
Regarding claim 13, Hezar teaches the semiconductor device of claim 1, wherein the N-type doped region and the P-type doped region comprise respective rings in the semiconductor substrate (Hezar, Fig 9, para. 32).
Regarding claim 14, Hezar teaches a circuit comprising: an avalanche photodiode having a cathode (Hezar, Fig. 7, 175), an anode (Hezar, Fig. 7, 171), a first field plate coupled to the cathode (Hezar, Fig. 7, 182), and a second field plate coupled to the anode (Hezar, Fig. 7, 181); and a bias circuit coupled to the first and second terminals (Hezar, para. 26).
Regarding claim 15, Hezar teaches the circuit of claim 14, wherein the avalanche photodiode comprises: a semiconductor substrate having a surface (Hezar, Fig 7, 120, para. 25);
an N-type doped region in the semiconductor substrate (Hezar Fig 7, 140, para. 25),
the N-type doped region electrically coupled to the cathode (Hezar Fig 7, 175);
a P-type doped region in the semiconductor substrate (Hezar, Fig. 7, 120, para. 23)
the P-type doped region electrically coupled to the anode (Hezar Fig 7. 171, par 29),
and the P-type doped region and the N-type doped region forming a first PN junction oriented along a first axis parallel to the surface (Hezar, Fig 7, 135, 140, 145, para. 13);
a second PN junction in the semiconductor substrate (Hezar, Fig 7, Junction 135, Para 13),
the second PN junction including one of the N-type or P-type doped regions and oriented along a second axis that intersects the surface (Hezar, Fig 7, Junction 135, 140, 145, Para 13).
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Regarding claim 17, Hezar teaches the circuit of claim 14, wherein the first and second field plates comprise polycrystalline silicon (Hezar, para. 29). NOTE: Hezar refers to the material as polysilicon, which a person having ordinary skill in the art before the filing date of the invention would recognize as a term for polycrystalline silicon.
Claim Rejections 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3, 5, 8-10, 16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hezar et. al. (US 20220352406), hereinafter referred to as Hezar, as applied above, and further in view of Takimoto et. al. (US 20200028019), hereinafter referred to as Takimoto.
Regarding claim 3, Hezar teaches the semiconductor device of claim 1, but does not teach wherein at least a portion of the first field plate is between the first terminal and the N-type doped region, and at least a portion of the second field plate is between the second terminal and the P-type doped region.
However, Takimoto teaches an avalanche photodiode wherein a portion of the field plates (Takimoto, Fig. 4, 9) is between the terminal (Takimoto, Fig. 4, A) and the P-type doped region (Takimoto Fig. 4, 7) to prevent edge breakdown (Takimoto, paras. 80-81. Takimoto also states (Takimoto para. 82) that the avalanche photodiode may be constituted with inverted polarities, which clearly provides the same results. Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to incorporate and modify the teachings of Takimoto and place the field plates between both the first and second terminals to prevent edge breakdown (Takimoto, para. 80-82).
Regarding claim 5, Hezar teaches the semiconductor device of claim 1, but does not teach a third terminal electrically coupled to the semiconductor substrate; a third field plate on the surface and electrically coupled to the third terminal; and a fourth field plate on the surface and electrically coupled to one of the first terminal or second terminal.
However, Takimoto teaches a third terminal (S), electrically coupled to the semiconductor substrate (Takimoto, Fig 4, 1). Takimoto also teaches two field plates attached to the terminal coupled to the P-typed doped region (Takimoto, Fig. 4, 9). Takimoto also discloses that the avalanche photodiode may be constituted with inverted polarities, which clearly provides the same results (Takimoto, para. 82). Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Hezar and Takimoto to place two field plates on the terminal coupled to the N-doped region, and further obvious to try placing field plates on the first and third terminals, which are coupled to P-doped regions, to prevent edge breakdown.
Regarding claim 8, Hezar teaches the semiconductor device of claim 2, but does not teach further comprising a dielectric layer over the N-type doped region and the P-type doped region, the first and second field plates in the dielectric layer.
However, Takimoto does teach a dielectric layer (Takimoto, Fig 4, 13) over the N-type doped region (Takimoto, Fig 4, 8) and the P-type doped region (Takimoto, Fig. 4, 7, 20), and having field plates in the dielectric layer (Takimoto, Fig. 4, 9). Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Hezar with the field plate placement of Takimoto and place the field plates in the dielectric layer, coupled to the terminals, to prevent edge breakdown.
Regarding claim 9, as best understood based on the 112(b) issue identified above, modified Hezar teaches the semiconductor device of claim 8. Takimoto further teaches that the material of the dielectric layer is silicon oxide (Fig 4, 13, para. 64). Silicon oxide is transparent to certain wavelengths.
Regarding claim 10, modified Hezar teaches the semiconductor device of claim 9, wherein the P-type doped region is a first P-type doped region (Takimoto, Fig. 4, 7, 2), and the semiconductor device further comprises a second P-type doped region under the portion of the dielectric layer that is transparent (Takimoto, Fig. 4, 20, 4), the second P-type doped region being part of the second PN junction (Takimoto, Fig 4, 4, 3, 2). Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Hezar and Takimoto to create the second P-doped region as part of a PN-junction to prevent edge breakdown.
Regarding claim 16, Hezar teaches the semiconductor device of claim 15, but does not teach wherein at least a portion of the first field plate is between the cathode and the N-type doped region, and at least a portion of the second field plate is between the anode and the P-type doped region.
However, Takimoto teaches placing field plates (Takimoto, Fig 4, 9) at least partially between the anode (Takimoto, Fig 4, A) and the P-type doped region (Takimoto, Fig 4, 2). Takimoto also states (Takimoto para. 82) that the avalanche photodiode may be constituted with inverted polarities, which clearly provides the same results. Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Hezar and Takimoto to put field plates on both the anode and the cathode, and place them between the anode and the P-doped region and between the cathode and the N-doped region to prevent edge breakdown (Takimoto para. 80-82).
Regarding claim 18, Hezar teaches an avalanche photodiode comprising: a semiconductor substrate having a surface (Hezar, Fig 7, 120); an N-type doped region in the semiconductor substrate (Hezar, Fig 7, 140, para. 25); a P-type doped region in the semiconductor substrate (Hezar, Fig. 7 120 – substrate is p-doped, para. 23), the P-type doped region and the N-type doped region forming a first PN junction oriented along a first axis parallel to the surface (Hezar, Fig 7, 140, 145, -Horizontal portion, para. 13); a second PN junction in the semiconductor substrate (Hezar, Fig. 7, 135, para 13-vertical portion), the second PN junction including one of the N-type or P-type doped regions and oriented along a second axis that intersects the surface(Hezar, Fig. 7, 135, para 13-vertical portion); a first terminal (175) electrically coupled to the N-type doped region (Hezar Fig 7, 175); a second terminal electrically (171) coupled to the P-type doped region(Hezar, Fig. 7, 171); a first conductive plate on the surface (Hezar Fig 7, 182 para. 29), the first conductive plate electrically coupled to the N-type doped region and extending over a first part of the semiconductor substrate between the N-type and P-type doped regions (Hezar Fig 7, 182, para 29); a second conductive plate on the surface (Hezar, Fig 7, 181, para. 29), the second conductive plate electrically coupled to the P-type doped region and extending over a second part of the semiconductor substrate between the N-type and P-type doped region (Hezar, Fig 7, 181, para 29), the first and second field plates being separated by a gap (Hezar, Fig 7, 181-182). Hezar does not teach a dielectric layer over the N-type doped region and the P-type doped region, the first and second conductive plates in the dielectric layer.
However, Takimoto does teach a dielectric layer (Takimoto, Fig. 4, 13), over the N-type doped region (Takimoto, Fig. 4, 8), and the P-type doped region (Takimoto, Fig. 4, 2, 7, 20), and the two conductive plates (Takimoto, Fig. 4, 9) electrically coupled to the anode (Takimoto, Fig. 4, A). Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Hezar and Takimoto by creating field plates electrically coupled to the P and N-typed doped regions within a dielectric layer to prevent edge breakdown.
Regarding claim 19, as best understood based on the 112(b) issue identified above, modified Hezar teaches the avalanche photodiode of claim 18 and further teaches wherein the P-type doped region is a first P-type doped region (Hezar, Fig. 7, 171), and the avalanche photodiode further comprises a second P-type doped region (Hezar, Fig. 7, 131) the second P-type doped region being part of the second PN junction (Hezar, Fig. 7). Hezar does not contain a dielectric layer.
However, Takimoto does contain a dielectric layer (Takimoto, Fig. 4, 13) over a PN junction (Takimoto, Fig. 4, 310, 2) and a second PN junction (Takimoto, Fig. 4, 6, 25, 2). Therefore it would have been obvious to one having ordinary skill in the art to combine the teachings of Hezar and Takimoto to create the photodiode of claim 19 to prevent edge breakdown (Takimoto, para. 80-82).
Regarding claim 20, modified Hezar teaches the avalanche photodiode of claim 18 and further teaches at least a portion of the second conductive plate is between the anode and the P-type doped region (Takimoto, Fig. 4, 9). It does not teach wherein at least a portion of the first conductive plate is between the cathode and the N-type doped region.
However, Takimoto also states (Takimoto para. 82) that the avalanche photodiode may be constituted with inverted polarities, which clearly provides the same results. Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Hezar and Takimoto to put field plates on both the anode and the cathode, and place them between the anode and the P-doped region and between the cathode and the N-doped region to prevent edge breakdown (Takimoto para. 80-82).
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Hezar et. al. (US 20220352406), hereinafter referred to as Hezar, as applied above in view of Takimoto et. al. (US 20200028019), hereinafter referred to as Takimoto and further in view of Shah et. al. (US 20220334231).
Regarding claim 11. as best understood based on the 112(b) issue identified above, modified Hezar teaches the semiconductor device of claim 8, but does not teach further comprising an optically-opaque layer over a portion of the dielectric layer containing the first and second field plates.
However, Shah teaches an avalanche photodiode (APD, ) including an optically-opaque layer (Shah, Fig. 29, 348) over a portion of the dielectric layer (Shah, Fig. 29, 342) containing the electrodes (Shah, Fig. 29, 343a, 343b). Therefore because modified Hezar teaches that the first and second field plates are electrically coupled to the electrodes, it would have been obvious to one having ordinary skill in the art to combine the teachings of Hezar, Takimoto and Shah to create the optically opaque layer over a portion of the dielectric layer containing the first and second field plates, to prevent damage to the photodiode (Shah, para. 231).
Regarding claim 12. modified Hezar teaches the semiconductor device of claim 11 and further teaches wherein the optically-opaque layer comprises a metal (Shah, para. 231).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mazillo (US. Pub. 20220406954 ) teaches a highly doped p-type polycrystalline semiconductor to reduce the electrical field at the edge of the PN junction.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:00-4:30.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893