Final Rejection
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Objections to the Specification
The disclosure is objected to because of the following informality:
In paragraph 22, it reads in part “PN junction 130 is oriented along an axis that intersects surface 130, where the P-type doped region 124 can be configured as a multiplication region.” This is objected to because 130 has already been identified as the PN junction. Paragraph 22 references Fig. 1. Fig. 1 shows PN junction 130 intersecting surface 103.
Appropriate correction is required.
NOTE: Examiner acknowledges that a new version of the specification was submitted. Examiner reviewed the new version and determined that the above informality was not corrected and may be found on page 6, line 11 of the submitted response.
Claim Rejections 35 USC § 112
Applicant’s arguments, see page 2, lines 1-24, filed 6/05/2026, with respect to claims 1, 2, 9, 10, 11 and 19 have been fully considered and are persuasive. The rejection of claims 1, 2, 9, 10, 11 and 19 has been withdrawn.
Claim Rejections 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 6, 7, 13-15 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hezar et. al. (US 20220352406), hereinafter referred to as Hezar.
Regarding claim 1, Hezar teaches a semiconductor device comprising: a semiconductor substrate having a surface (Hezar, 120, Fig. 7) ; an N-type doped region in the semiconductor substrate (Hezar, 140, Fig. 7, para. 25); a P-type doped region in the semiconductor substrate (Hezar, 120, Fig 7, para. 18), the P-type doped region and the N-type doped region forms a first PN junction oriented along a first axis parallel to the surface (Hezar, Junction 135, 140, 145, Fig 7, Para 13); a lightly-doped region in the semiconductor substrate and between the N-type doped region and the P-type doped region (Hezar, 123, Fig. 7, paras. 18-19); a second PN junction in the semiconductor substrate, the PN junction including one of the N-type or P-type doped regions and oriented along a second axis that intersects the surface (Hezar, Junction 135, 140, 145, Fig 7, Para 13); a first terminal (Hezar, 175 Fig. 7) electrically coupled to the N-type doped region (Hezar, Fig 7); a second terminal (Hezar, 171, Fig. 7) electrically coupled to the P-type doped region (Hezar, Fig 7); a first field plate (Hezar, 182, Fig. 7, para. 29) on the surface, the first field plate electrically coupled to the first terminal and extending over a first part of the lightly doped region (Hezar, Fig 7); and a second field plate (Hezar, 181, Fig. 7, para. 29) on the surface, the second field plate electrically coupled to the second terminal and extending over a second part of the lightly doped region (Hezar, Fig 7), the first and second field plates being separated by a gap over the lightly- doped region. (Hezar, Fig 7).
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Regarding claim 4, Hezar teaches the semiconductor device of claim 1, wherein the first and second field plates comprise polycrystalline silicon (Hezar, para. 29). NOTE: Hezar refers to the material as polysilicon, which a person having ordinary skill in the art before the filing date of the invention would recognize as a term for polycrystalline silicon.
Regarding claim 6, Hezar teaches the semiconductor device of claim 1, wherein the second PN junction is part of an avalanche photodiode (Hezar, paras 26-28).
Regarding claim 7, Hezar teaches the semiconductor device of claim 6, wherein the first terminal is a cathode of the avalanche photodiode (Hezar, para. 23, 29), and the second terminal is an anode of the avalanche photodiode (Hezar, para. 23).
Regarding claim 13, Hezar teaches the semiconductor device of claim 1, wherein the N-type doped region and the P-type doped region comprise respective rings in the semiconductor substrate (Hezar, Fig 9, para. 32).
Regarding claim 14, Hezar teaches a circuit comprising: an avalanche photodiode having a cathode (Hezar, 175, Fig. 7, para. 23), an anode (Hezar, 171, Fig. 7, para. 23), a first field plate coupled to the cathode (Hezar, 182, Fig. 7, para. 23), and a second field plate coupled to the anode (Hezar, Fig. 181, 7, para. 23); the first field plate and the second field plate each at least partially overlapping a lightly-doped semiconductor region (Hezar, 123, Fig. 7, paras. 18-19) between the cathode and the anode; and a bias circuit coupled to the anode and the cathode (Hezar, para. 26).
Regarding claim 15, Hezar teaches the circuit of claim 14, wherein the avalanche photodiode comprises: a semiconductor substrate having a surface (Hezar, 120, Fig 7, para. 25);
an N-type doped region in the semiconductor substrate (Hezar, 140, Fig 7, para. 25),
the N-type doped region electrically coupled to the cathode (Hezar 175, Fig 7, para. 23);
a P-type doped region in the semiconductor substrate (Hezar, 120, Fig. 7, para. 23)
the P-type doped region electrically coupled to the anode (Hezar 171, Fig 7, par 29),
and the P-type doped region and the N-type doped region forming a first PN junction oriented along a first axis parallel to the surface (Hezar, 135, 140, 145, Fig 7, para. 13);
and the lightly-doped semiconductor region between the N-type doped region and the P-type doped region in the semiconductor substrate (Hezar, Fig. 7);
and a second PN junction in the semiconductor substrate (Hezar, Junction 135, Fig 7, Para 13),
the second PN junction including one of the N-type or P-type doped regions and oriented along a second axis that intersects the surface (Hezar, Junction 135, 140, 145, Fig 7, Para 13).
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Regarding claim 17, Hezar teaches the circuit of claim 14, wherein the first and second field plates comprise polycrystalline silicon (Hezar, para. 29). NOTE: Hezar refers to the material as polysilicon, which a person having ordinary skill in the art before the filing date of the invention would recognize as a term for polycrystalline silicon.
Claim Rejections 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3, 5, and 8-10are rejected under 35 U.S.C. 103 as being unpatentable over Hezar as applied to claim 1 above, and further in view of Takimoto et. al. (US 20200028019), hereinafter referred to as Takimoto.
Regarding claim 3, Hezar teaches the semiconductor device of claim 1, but does not teach wherein at least a portion of the first field plate is between the first terminal and the N-type doped region, and at least a portion of the second field plate is between the second terminal and the P-type doped region.
However, Takimoto teaches an avalanche photodiode wherein a portion of the field plates (Takimoto, 9 Fig. 4, para. 62) is between the terminal (Takimoto, A Fig. 4, para. 64 ) and the P-type doped region (Takimoto, 7, Fig. 4, para. 63) to prevent edge breakdown (Takimoto, paras. 80-81). Takimoto also states (Takimoto para. 82) that the avalanche photodiode may be constituted with inverted polarities, which clearly provides the same results. Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to incorporate and modify the teachings of Takimoto and place the field plates between both the first and second terminals to prevent edge breakdown (Takimoto, para. 80-82).
Regarding claim 5, Hezar teaches the semiconductor device of claim 1, but does not teach a third terminal electrically coupled to the semiconductor substrate; a third field plate on the surface and electrically coupled to the third terminal; and a fourth field plate on the surface and electrically coupled to one of the first terminal or the second terminal.
However, Takimoto teaches a third terminal (S), electrically coupled to the semiconductor substrate (Takimoto, 1 Fig 4, para. 53). Takimoto also teaches two field plates attached to the terminal coupled to the P-typed doped region (Takimoto, 9, Fig. 4). Takimoto also discloses that the avalanche photodiode may be constituted with inverted polarities, which clearly provides the same results (Takimoto, para. 82). Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Hezar and Takimoto to place two field plates on the terminal coupled to the N-doped region, and further obvious to try placing field plates on the first and third terminals, which are coupled to P-doped regions, to prevent edge breakdown.
Regarding claim 8, Hezar teaches the semiconductor device of claim 1, but does not teach further comprising a dielectric layer over the N-type doped region and the P-type doped region, the first and second field plates in the dielectric layer.
However, Takimoto does teach a dielectric layer (Takimoto, 13, Fig 4, para. 64) over the N-type doped region (Takimoto, 8, Fig 4, para. 63) and the P-type doped region (Takimoto, 7, 20, Fig. 4, para. 63), and having field plates in the dielectric layer (Takimoto, 9, Fig. 4). Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Hezar with the field plate placement of Takimoto and place the field plates in the dielectric layer, coupled to the terminals, to prevent edge breakdown.
Regarding claim 9, modified Hezar teaches the semiconductor device of claim 8. Takimoto further teaches that the material of the dielectric layer is silicon oxide (Takimoto, 13. Fig 4, para. 64). Silicon oxide is transparent to certain wavelengths.
Regarding claim 10, modified Hezar teaches the semiconductor device of claim 9, wherein the P-type doped region is a first P-type doped region (Takimoto, 7, 2, Fig. 4, paras. 51, 63 ), and the semiconductor device further comprises a second P-type doped region under the portion of the dielectric layer that is transparent (Takimoto, 20, 4, Fig. 4, para. 56, 63), the second P-type doped region being part of the second PN junction (Takimoto, 4, 3, 2, Fig 4). Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Hezar and Takimoto to create the second P-doped region as part of the second PN-junction to prevent edge breakdown.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Hezar as applied to claim 15, and further in view of Takimoto.
Regarding claim 16, Hezar teaches the semiconductor device of claim 15, but does not teach wherein at least a portion of the first field plate is between the cathode and the N-type doped region, and at least a portion of the second field plate is between the anode and the P-type doped region.
However, Takimoto teaches placing field plates (Takimoto, 9, Fig. 4, para. 62) at least partially between the anode (Takimoto, A, Fig 4) and the P-type doped region (Takimoto, 2, Fig 4). Takimoto also states (Takimoto para. 82) that the avalanche photodiode may be constituted with inverted polarities, which clearly provides the same results. Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Hezar and Takimoto to put field plates on both the anode and the cathode, and place them between the anode and the P-doped region and between the cathode and the N-doped region to prevent edge breakdown (Takimoto para. 80-82).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hezar, and Takimoto.
Regarding claim 18, Hezar teaches an avalanche photodiode comprising: a semiconductor substrate having a surface (Hezar, 120, Fig 7, para. 19); an N-type doped region in the semiconductor substrate (Hezar, 140 Fig 7, para. 25); a P-type doped region in the semiconductor substrate (Hezar, 120, Fig. 7, substrate is p-doped, para. 23), the P-type doped region and the N-type doped region forming a first PN junction oriented along a first axis parallel to the surface (Hezar, 140, 145, -Horizontal portion, Fig. 7 para. 13); a lightly-doped region (Hezar, 123, Fig. 7, paras. 18-19) in the semiconductor substrate and between the N-type doped region and the P-type doped region; a second PN junction in the semiconductor substrate (Hezar, 135, Fig. 7, para 13-vertical portion), the second PN junction including one of the N-type or P-type doped region and oriented along a second axis that intersects the surface (Hezar, 135, Fig. 7, para 13-vertical portion); a first terminal (Hezar, 175, Fig. 7, para. 23) electrically coupled to the N-type doped region (Hezar 175, Fig 7, para. 23); a second terminal electrically (Hezar, 171, Fig. 7, para. 23) coupled to the P-type doped region (Hezar, 171, Fig. 7, para. 23); a first conductive plate on the surface (Hezar, 182, Fig 7, para. 29), the first conductive plate electrically coupled to the N-type doped region and extending over a first part of the lightly doped region (Hezar Fig 7); a second conductive plate on the surface (Hezar, 181, Fig 7, para. 29), the second conductive plate electrically coupled to the P-type doped region and extending over a second part of the lightly doped region, the first and second conductive plates being separated by a gap (Hezar, 181-182, Fig 7) over the lightly doped region. Hezar does not teach a dielectric layer over the N-type doped region and the P-type doped region, the first and second conductive plates in the dielectric layer.
However, Takimoto does teach a dielectric layer (Takimoto, 13, Fig. 4, para. 64), over the N-type doped region (Takimoto, 8, Fig. 4, para. 63), and the P-type doped region (Takimoto, 2, 7, 20, Fig. 4, paras. 51, 63), and the two conductive plates (Takimoto, 9, Fig. 4, para. 62) electrically coupled to the anode (Takimoto, A, Fig. 4, para. 64). Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Hezar and Takimoto by creating field plates electrically coupled to the P and N-typed doped regions within a dielectric layer to prevent edge breakdown.
Regarding claim 19, modified Hezar teaches the avalanche photodiode of claim 18 wherein the P-type doped region is a first P-type doped region (Hezar, Fig. 7, 171), and the avalanche photodiode further comprises a second P-type doped region (Hezar, Fig. 7, 131) under a portion of the dielectric layer (Takimoto, 13, Fig. 4, para. 64) that is transparent (Takimoto teaches that the material of the dielectric layer is silicon oxide (Takimoto, 13, Fig 4, para. 64). Silicon oxide is transparent to certain wavelengths.), the second P-type doped region being part of the second PN junction (Hezar, Fig. 7).
Regarding claim 20, modified Hezar teaches the avalanche photodiode of claim 18 and further teaches at least a portion of the second conductive plate is between the first terminal and the P-type doped region (Takimoto, 9, Fig. 4, para. 62). It does not teach wherein at least a portion of the first conductive plate is between the second terminal and the N-type doped region.
However, Takimoto also states (Takimoto para. 82) that the avalanche photodiode may be constituted with inverted polarities, which clearly provides the same results. Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the teachings of Hezar and Takimoto to put field plates on both the anode and the cathode, and place them between the anode and the P-doped region and between the cathode and the N-doped region to prevent edge breakdown (Takimoto para. 80-82).
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Hezar, as and Takimoto as applied to claim 8 further in view of Shah et. al. (US 20220334231), hereinafter referred to as Shah.
Regarding claim 11. Hezar teaches the semiconductor device of claim 8, but does not teach further comprising an optically-opaque layer over a portion of the dielectric layer containing the first and second field plates.
However, Shah teaches an avalanche photodiode (APD, ) including an optically-opaque layer (Shah, Fig. 29, 348) over a portion of the dielectric layer (Shah, Fig. 29, 342) containing the electrodes (Shah, Fig. 29, 343a, 343b). Therefore because modified Hezar teaches that the first and second field plates are electrically coupled to the electrodes, it would have been obvious to one having ordinary skill in the art to combine the teachings of Hezar, Takimoto and Shah to create the optically opaque layer over a portion of the dielectric layer containing the first and second field plates, to prevent damage to the photodiode (Shah, para. 231).
Regarding claim 12. modified Hezar teaches the semiconductor device of claim 11 and further teaches wherein the optically-opaque layer comprises a metal (Shah, para. 231).
Claim 21 rejected under 35 U.S.C. 103 as being unpatentable over Hezar, as and Takimoto as applied to claim 18, and further in view of Shah.
Regarding claim 21, modified Hezar teaches the semiconductor device of claim1 8, but does not teach further comprising an optically-opaque layer over the first and second plates.
However, Shah teaches an avalanche photodiode (APD, ) including an optically-opaque layer (Shah, Fig. 29, 348) over a portion of the dielectric layer (Shah, Fig. 29, 342) containing the electrodes (Shah, Fig. 29, 343a, 343b). Therefore because modified Hezar teaches that the first and second conductive plates are electrically coupled to the electrodes, it would have been obvious to one having ordinary skill in the art to combine the teachings of Hezar, Takimoto and Shah to create the optically opaque layer over the first and second field conductive, to prevent damage to the photodiode (Shah, para. 231).
Response to Arguments
Applicant's arguments filed 5 June 2026 have been fully considered but they are not persuasive. Applicant amened claims 1, to read in part :
“a lightly-doped region in the semiconductor substrate and between the N-type doped region and the P-type doped region; ...a first field plate on the surface, the first field plate electrically coupled to the first terminal and extending over a first part of the lightly-doped region; and a second field plate on the surface, the second field plate electrically coupled to the second terminal and extending over a second part of the lightly- doped region, the first and second field plates being separated by a gap over the lightly-doped region.”
Applicant also amend claim 14 to read in part "an avalanche photodiode having a cathode, an anode, a first field plate coupled to the cathode, and a second field plate coupled to the anode, the first field plate and the second field plate each at least partially overlapping a lightly-doped semiconductor region between the cathode and the anode."
Claim 18 was similarly amended to include “a lightly-doped region in the semiconductor substrate and between the N-type doped region and the P-type doped region;” and “the first and second conductive plates being separated by a gap over the lightly-doped region.”
Applicant stated that the references cited in the Office Action are not alleged to, and indeed do not, render these features of claim 1, 14, or 18 unpatentable. However, as described in the claim rejections above, Hezar does render these features unpatentable. As shown in Hezar Fig. 7, the lightly-doped separation portion 123 is situated laterally between the N-type cathode 140 and the P-type epitaxial layer 120/buried layer 132. Furthermore, Fig. 7 clearly depicts the gap between field plates 181 and 182 is positioned directly over the isolation structure 160, which in turn is directly over the lightly-doped region 123.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fischer (US Pub, 20200251587) teaches a diode that uses field plates.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:30-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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