Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2026-02-10 has been entered.
Response to Amendment
The amendment filed on 2026-02-10 has been entered. Claim(s) 1-11 remain pending in this application. Claim(s) 1 and 10 have been amended. Claim(s) 11 has/have been newly added.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 10, 11 and their dependents have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chao et al. (US-20090224780-A1).
Regarding Claim 1, Chao teaches a probe card structure for high frequency test, comprising:
a circuit board (Fig 8: circuit board, 20);
a silicon substrate (Fig 8: silicon membrane, 30) disposed on a side of the circuit board and electrically connected to the circuit board (Fig 8 has arrow indicating the substrate, 30 is moved in contact with the circuit board, 20. Fig 4 also shows an embodiment where the substrate, 30 and the circuit board are in contact), the silicon substrate including a signal processing circuit embedded in the silicon substrate (Fig 8: active test control circuitry, 91 | Para [0042] teaches 91 may be RLC components, buffers, amplifiers), the signal processing circuit being configured to process a high frequency signal from a device under test and generate an output signal for transmitting to a tester (Para [0003] teaches that testing involves receiving signals generated from the DUT and those signals are analyzed by automatic test equipment, and Para [0042] teaches using high frequency test components, Fig 8 shows electrical contact, 23, and Para [0027] teaches these are for mating to automatic test equipment); and
a probe head assembly including a plurality sets of probes (Fig 8: probes, 60 | refer to annotated Fig 8 of Chao), each probe having one end connected to the signal processing circuit and another end configured to contact the device under test (Fig 8: DUT, 51 | connections can be seen in Fig 8), configured to receive the high frequency signal from the device under test and transmit the high frequency signal therefrom to the silicon substrate (Para [0003] teaches that testing involves receiving signals generated from the DUT and Para [0042] teaches using high frequency test components).
Regarding Claim 2, Chao teaches The probe card structure according to claim 1, wherein the signal processing circuit is an active component or a passive component (Para [0042] teaches that the circuitry, 91, may be active (amplifier) or passive (RLC) components).
Regarding Claim 3, Chao teaches The probe card structure according to claim 1, wherein the signal processing circuit includes a power supply, an amplifier, an oscillator, a digital signal processor, or an analog signal converter (Para [0042] teaches the circuitry, 91, may include an amplifier).
Regarding Claim 4, Chao teaches The probe card structure according to claim 1, wherein the signal processing circuit includes a first circuit element, a second circuit element, and a third circuit element (Para [0042] teaches the circuitry, 91, may be RLC components, where each of the resistor, inductor and capacitor would be a circuit element).
Regarding Claim 5, Chao teaches The probe card structure according to claim 1, wherein each of the plurality sets of probes has a first contact end and a second contact end that are opposite to each other, the first contact end is electrically connected to the silicon substrate, the second contact end is in contact with the device under test (can be seen in Fig 8), and
the silicon substrate and the device under test have a same material property (the DUT, 51, and the silicon membrane, 30, are in electrical communication and therefore must have a same material property to enable communication).
Regarding Claim 6, Chao teaches The probe card structure according to claim 5, wherein an electrical signal from the device under test is processed by the signal processing circuit on the silicon substrate without passing through the circuit board (can be seen in Fig 8).
Regarding Claim 7, Chao teaches The probe card structure according to claim 1, wherein a pitch between two probes is less than 40 pm (Para [0040] defines a fine pitch as between 20 to 50 microns and Para [0043] teaches the spacing between the probes, 60, may have a fine pitch).
Regarding Claim 8, Chao teaches The probe card structure according to claim 1, wherein a surface of the silicon substrate facing the circuit board is provided with a plurality of solder balls (Fig 8: solder balls, 33), and a material of each of the plurality of solder balls is metal or alloy (solder, by definition, is a metal alloy).
Regarding Claim 9, Chao teaches The probe card structure according to claim 1, wherein each of the plurality sets of probes is made of a material selected from a group consisting copper, palladium, silver, gold, platinum, tungsten, germanium, tungsten-rhenium alloy, beryllium copper alloy, palladium gold alloy, palladium silver alloy, tungsten carbide, and alloys thereof (Para [0036] teaches that the probe tips may be made of tungsten).
Regarding Claim 10, Chao teaches a method for testing high frequency signal, comprising:
receiving a high frequency signal from a device under test using a probe head assembly (Para [0003] teaches that testing involves receiving signals generated from the DUT and those signals are analyzed by automatic test equipment, and Para [0042] teaches using high frequency test components); wherein the probe head assembly includes a plurality sets of probes (Fig 8: probes, 60 | refer to annotated Fig 8 of Chao), each probe having one end connected to a signal processing circuit embedded in a silicon substrate (Fig 8: active test control circuitry, 91 | Para [0042] teaches 91 may be RLC components, buffers, amplifiers) and another end configured to contact the device under test (can be seen in Fig 8 | connections can be seen in Fig 8), for transmitting the high frequency signal to the silicon substrate (Para [0003] teaches that testing involves receiving signals generated from the DUT and Para [0042] teaches using high frequency test components); and
processing the high frequency signal into an output signal using the signal processing circuit, and transmitting the output signal to a tester (Para [0003] teaches that testing involves receiving signals generated from the DUT and those signals are analyzed by automatic test equipment, and Para [0042] teaches using high frequency test components, Fig 8 shows electrical contact, 23, and Para [0027] teaches these are for mating to automatic test equipment).
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Annotated Figure 8 of Chao
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chao in view of Yu (CN-112904177-A).
Regarding Claim 11, Chao teaches a probe card structure for high frequency test, comprising:
a circuit board (Fig 8: circuit board, 20);
a silicon substrate (Fig 8: silicon membrane, 30) disposed on a side of the circuit board and electrically connected to the circuit board (Fig 8 has arrow indicating the substrate, 30 is moved in contact with the circuit board, 20. Fig 4 also shows an embodiment where the substrate, 30 and the circuit board are in contact), the silicon substrate including a signal processing circuit embedded in the silicon substrate (Fig 8: active test control circuitry, 91 | Para [0042] teaches 91 may be RLC components, buffers, amplifiers), the signal processing circuit being configured to process a high frequency signal from a device under test and generate an output signal for transmitting to a tester (Para [0003] teaches that testing involves receiving signals generated from the DUT and those signals are analyzed by automatic test equipment, and Para [0042] teaches using high frequency test components, Fig 8 shows electrical contact, 23, and Para [0027] teaches these are for mating to automatic test equipment); and
a probe head assembly including a plurality sets of probes (Fig 8: probes, 60 | refer to annotated Fig 8 of Chao), each having one end connected to the signal processing circuit and another end configured to contact the device under test (Fig 8: DUT, 51 | connections can be seen in Fig 8), configured to receive the high frequency signal from the device under test and transmit the high-frequency signal therefrom to the silicon substrate (Para [0003] teaches that testing involves receiving signals generated from the DUT and Para [0042] teaches using high frequency test components).
Chao does not teach wherein the probe head assembly comprises a main body having two opposing sides, an upper guide plate, and a lower guide plate respectively disposed on the two opposing sides of the main body,
wherein each of the plurality sets of probes has a straight body arranged perpendicular to the upper and the lower guide plates,
wherein the upper guide plate and the lower guide plate are arranged parallel to each other, and each has a plurality of guide holes configured to cooperatively retain the plurality sets of probes. However, Yu teaches wherein the probe head assembly comprises a main body having two opposing sides (Fig 1: middle guide plate, 1-2), an upper guide plate, and a lower guide plate respectively disposed on the two opposing sides of the main body (Fig 1: guide plates, 1-1 & 1-3),
wherein each of the plurality sets of probes (Fig 1: probe, 1-4) has a straight body arranged perpendicular to the upper and the lower guide plates (can be seen in Fig 1),
wherein the upper guide plate and the lower guide plate are arranged parallel to each other (can be seen in Fig 1), and each has a plurality of guide holes configured to cooperatively retain the plurality sets of probes (can be seen in Fig 1). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the probe head of Chao to incorporate the guides of Yu. A motivation for this modification is to ensure proper alignment of the probes.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEREMIAH J BARRON whose telephone number is (571)272-0902. The examiner can normally be reached M-F 09:30-17:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak can be reached at (571) 270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JEREMIAH J BARRON/Examiner, Art Unit 2858
/LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858