Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 2026-06-25 has been entered. Claim(s) 1-9 remain pending in this application. Claim(s) 1 has been amended. Claim(s) 10-11 have been canceled.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and its dependents have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Chao et al. (US-20090224780-A1) in view of Lee et al. (US-202000300893-A1).
Regarding Claim 1, Chao teaches a probe card structure for high frequency test, comprising:
a circuit board (Fig 8: circuit board, 20);
a silicon substrate (Fig 8: silicon membrane, 30) disposed on a side of the circuit board and electrically connected to the circuit board (Fig 8 has arrow indicating the substrate, 30 is moved in contact with the circuit board, 20. Fig 4 also shows an embodiment where the substrate, 30 and the circuit board are in contact), the silicon substrate including a signal processing circuit embedded in the silicon substrate (Fig 8: active test control circuitry, 91 | Para [0042] teaches 91 may be RLC components, buffers, amplifiers), the signal processing circuit being configured to process a high frequency signal from a device under test and generate an output signal for transmitting to a tester (Para [0003] teaches that testing involves receiving signals generated from the DUT and those signals are analyzed by automatic test equipment, and Para [0042] teaches using high frequency test components, Fig 8 shows electrical contact, 23, and Para [0027] teaches these are for mating to automatic test equipment); and
a probe head assembly including a plurality sets of probes (Fig 8: probes, 60 | refer to annotated Fig 8 of Chao), each probe having one end connected to the signal processing circuit and another end configured to contact the device under test (Fig 8: DUT, 51 | connections can be seen in Fig 8), configured to receive the high frequency signal from the device under test and transmit the high frequency signal therefrom to the silicon substrate (Para [0003] teaches that testing involves receiving signals generated from the DUT and Para [0042] teaches using high frequency test components).
Chao does not teach wherein the probe head assembly comprises a main body having two opposing sides, an upper guide plate, and a lower guide plate respectively disposed on the two opposing sides of the main body,
wherein each of the plurality sets of probes has a straight body arranged perpendicular to the upper and the lower guide plates,
wherein the upper guide plate and the lower guide plate are arranged parallel to each other, and each has a plurality of guide holes configured to cooperatively retain the plurality sets of probes,
wherein no interposer is provided between the upper guide plate and the silicon substrate, and wherein an end of each probe extends out of the upper guide plate to electrically connect with the signal processing circuit of the silicon substrate.
However, Lee teaches wherein the probe head assembly comprises a main body having two opposing sides (Fig 1: combination of spacer, 5, grounding sheet, 2, and spacing pad, 3), an upper guide plate(Fig 1: upper die, 1), and a lower guide plate (Fig 1: lower die, 4) respectively disposed on the two opposing sides of the main body (Can be seen in Fig 1),
wherein each of the plurality sets of probes has a straight body arranged perpendicular to the upper and the lower guide plates (Fig 1: plurality of conductive probes, 6),
wherein the upper guide plate and the lower guide plate are arranged parallel to each other (can be seen in Fig 1), and each has a plurality of guide holes configured to cooperatively retain the plurality sets of probes (Fig 1: thru-holes, 11 & 41),
wherein no interposer is provided between the upper guide plate and the silicon substrate (the combination of the probe head of Lee and the structure of Chao would have the probe tips (614) extending out from the upper die, 1, of Lee and contacting the silicon membrane, 30, of Chao, and therefore no interposer is located between in the combination), and
wherein an end of each probe extends out of the upper guide plate (Can be seen in Fig 1) to electrically connect with the signal processing circuit of the silicon substrate (Would be provided in the combination). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the probe head of Chao to include the body and guide plates of Lee. A motivation for this modification is to ensure proper alignment of the probes.
Regarding Claim 2, Chao further teaches wherein the signal processing circuit is an active component or a passive component (Para [0042] teaches that the circuitry, 91, may be active (amplifier) or passive (RLC) components).
Regarding Claim 3, Chao further teaches wherein the signal processing circuit includes a power supply, an amplifier, an oscillator, a digital signal processor, or an analog signal converter (Para [0042] teaches the circuitry, 91, may include an amplifier).
Regarding Claim 4, Chao further teaches wherein the signal processing circuit includes a first circuit element, a second circuit element, and a third circuit element (Para [0042] teaches the circuitry, 91, may be RLC components, where each of the resistor, inductor and capacitor would be a circuit element).
Regarding Claim 5, Chao further teaches wherein each of the plurality sets of probes has a first contact end and a second contact end that are opposite to each other, the first contact end is electrically connected to the silicon substrate, the second contact end is in contact with the device under test (can be seen in Fig 8), and
the silicon substrate and the device under test have a same material property (the DUT, 51, and the silicon membrane, 30, are in electrical communication and therefore must have a same material property to enable communication).
Regarding Claim 6, Chao further teaches wherein an electrical signal from the device under test is processed by the signal processing circuit on the silicon substrate without passing through the circuit board (can be seen in Fig 8).
Regarding Claim 7, Chao further teaches wherein a pitch between two probes is less than 40 pm (Para [0040] defines a fine pitch as between 20 to 50 microns and Para [0043] teaches the spacing between the probes, 60, may have a fine pitch).
Regarding Claim 8, Chao further teaches wherein a surface of the silicon substrate facing the circuit board is provided with a plurality of solder balls (Fig 8: solder balls, 33), and a material of each of the plurality of solder balls is metal or alloy (solder, by definition, is a metal alloy).
Regarding Claim 9, Chao further teaches wherein each of the plurality sets of probes is made of a material selected from a group consisting copper, palladium, silver, gold, platinum, tungsten, germanium, tungsten-rhenium alloy, beryllium copper alloy, palladium gold alloy, palladium silver alloy, tungsten carbide, and alloys thereof (Para [0036] teaches that the probe tips may be made of tungsten).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEREMIAH J BARRON whose telephone number is (571)272-0902. The examiner can normally be reached M, T, Th, F 10:30-17:00 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak can be reached at (571) 270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JEREMIAH J BARRON/Examiner, Art Unit 2858
/DANIEL R MILLER/Primary Examiner, Art Unit 2858
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