DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/15/2023, 11/21/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4, 13-18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son (US 2021/0183862) in view of Kim (US 2022/0005809).
Regarding claim 1, Son discloses, in at least figures 4, 7-21, and related text, a method for forming a semiconductor structure, comprising:
forming a stack (SS, [82]) on a substrate (SUB, [82]), wherein the stack (SS, [82]) comprises interlayer insulating layers (IL1, [82]) and sacrifice layers (IL2/SL/IL3, [82]) alternately stacked in a first direction (D3, figures), the stack (SS, [82]) comprises a plurality of storage regions (region of transistor/DS, [33], [62]) arranged at intervals in a second direction (D1, figures), the first direction (D3, figures) is perpendicular to a top surface of the substrate (SUB, [82]), and the second direction (D1, figures) is parallel to the top surface of the substrate (SUB, [82]);
forming first trenches (TR1, [93]) located between adjacent interlayer insulating layers (IL1, [82]) through removing part of the sacrifice layers (IL2/SL/IL3, [82]) of the storage regions (region of transistor/DS, [33], [62]);
forming transistor structures (SP/GI/GE, [97]) in the first trenches (TR1, [93]), wherein the transistor structures (SP/GI/GE, [97]) comprise gate layers (GI/GE, [97]) covering inner walls of the first trenches (TR1, [93]) and active structures (SP, [97]) located in the gate layers (GI/GE, [97]); and
forming a word line (WL, [70]) extending in the second direction (D1, figures).
Son does not explicitly disclose the word line envelops the gate layers of the plurality of storage regions arranged at intervals in the second direction.
Kim teaches, in at least figures 9A, 9B, and related text, the method comprising the word line (WL, [46]) envelops the gate layers (lower layer of WL/GD, [46], [47]) of the plurality of storage regions (region of CAP, [48]) arranged at intervals in the second direction (D3, figures), for the purpose of providing three-dimensional memory device with an improved integration degree ([4]).
Son and Kim are analogous art because they both are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Son with the specified features of Kim because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Son to have the word line envelops the gate layers of the plurality of storage regions arranged at intervals in the second direction, as taught by Kim, for the purpose of providing three-dimensional memory device with an improved integration degree ([4], Kim).
Regarding claim 2, Son in view of Kim discloses the method for forming a semiconductor structure according to claim 1 as described above.
Son further discloses, in at least figures 4, 7-21, and related text, providing the substrate (SUB, [82]); and
alternately depositing the interlayer insulating layers (IL1, [82]) and the sacrifice layers (IL2/SL/IL3, [82]) on the top surface of the substrate (SUB, [82]) in the first direction (D3, figures), wherein the sacrifice layers (IL2/SL/IL3, [82]) comprise first sacrifice layers (IL2, [82]), second sacrifice layers (SL, [82]) and third sacrifice layers (IL3, [82]) stacked in sequence in the first direction (D3, figures).
Regarding claim 4, Son in view of Kim discloses the method for forming a semiconductor structure according to claim 2 as described above.
Son further discloses, in at least figures 4, 7-21, and related text, before forming the first trenches (TR1, [93]) between adjacent interlayer insulating layers (IL1, [82]), the method further comprises:
etching the stack (SS, [82]) to form isolation trenches (H01/H02, [85]) located between the storage regions (region of transistor/DS, [33], [62]) adjacent in the second direction (D1, figures); and
forming isolation layers (VIP1/VIP2, [64]) filling up the isolation trenches (H01/H02, [85]).
Regarding claim 13, Son in view of Kim discloses the method for forming a semiconductor structure according to claim 1 as described above.
Son does not explicitly disclose a material of the active structures is an oxide semiconductor material.
Kim teaches, in at least figures 9A, 9B, and related text, the method comprising a material of the active structures (ACT, [45]) is an oxide semiconductor material ([45]), for the purpose of improving mobility of electron thereby improving operation speed of device.
Son and Kim are analogous art because they both are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Son with the specified features of Kim because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Son to have the material of the active structures being an oxide semiconductor material, as taught by Kim, for the purpose of improving mobility of electron thereby improving operation speed of device.
Regarding claim 14, Son discloses, in at least figures 4, 7-8C, and related text, a semiconductor structure, comprising:
a substrate (SUB, [82]);
a stacked structure (SS, [76]) located on the substrate (SUB, [82]), the stacked structure (SS, [76]) comprising a plurality of memory units (SP/GI/GE/DS, [33], [97]) arranged at intervals in a first direction (D3, figures) and in a second direction (D1, figures), and interlayer insulating layers (IL1, [82]) located between adjacent memory units (SP/GI/GE/DS, [33], [97]) in the first direction (D3, figures), the memory units (SP/GI/GE/DS, [33], [97]) comprising transistor structures (SP/GI/GE, [97]), the transistor structures (SP/GI/GE, [97]) comprising active structures (SP, [97]), and gate layers (GI/GE, [97]) distributed around peripheries of the active structures (SP, [97]), wherein the first direction (D3, figures) is perpendicular to a top surface of the substrate (SUB, [82]), the second direction (D1, figures) is parallel to the top surface of the substrate (SUB, [82]); and
a word line (WL, [70]) extending in the second direction (D1, figures).
Son does not explicitly disclose the word line enveloping gate layers of a plurality of memory units arranged at intervals in the second direction.
Kim teaches, in at least figures 9A, 9B, and related text, the device comprising the word line (WL, [46]) enveloping gate layers (lower layer of WL/GD, [46], [47]) of a plurality of memory units (MC, [100]) arranged at intervals in the second direction (D3, figures), for the purpose of providing three-dimensional memory device with an improved integration degree ([4]).
Son and Kim are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Son with the specified features of Kim because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Son to have the word line enveloping gate layers of a plurality of memory units arranged at intervals in the second direction, as taught by Kim, for the purpose of providing three-dimensional memory device with an improved integration degree ([4], Kim).
Regarding claim 15, Son in view of Kim discloses the semiconductor structure according to claim 14 as described above.
Son further discloses, in at least figures 4, 7-8C, and related text, the active structures (SP, [97]) are solid structures (figures); or the active structures are hollow structures.
Regarding claim 16, Son in view of Kim discloses the semiconductor structure according to claim 15 as described above.
Son does not explicitly disclose the active structure are hollow structures; the active structures comprise channel layers, and first active layers and second active layers located on opposite sides of the channel layers in a third direction, the third direction is parallel to the top surface of the substrate; the transistor structures further comprise: insulating filling layers, the active structures being distributed around peripheries of the insulating filling layers; wherein a thickness of the insulating filling layers is greater than or equal to a thickness of the channel layers in the first direction.
Kim teaches, in at least figures 3B, 4, 9A, 9B, and related text, the device comprising the active structure (ACT, [54]) are hollow structures (figures); the active structures (ACT, [54]) comprise channel layers (CH, [54]), and first active layers (SD1, [54]) and second active layers (SD1, [54]) located on opposite sides of the channel layers (CH, [54]) in a third direction (D2, figures), the third direction (D2, figures) is parallel to the top surface of the substrate (LS, [40]); the transistor structures further comprise: insulating filling layers (GM, [48]), the active structures (ACT, [54]) being distributed around peripheries of the insulating filling layers (GM, [48]); wherein a thickness of the insulating filling layers (GM, [48]) is greater than or equal to a thickness of the channel layers (CH, [54]) in the first direction (D1, figures), for the purpose of improving control of gate for channel.
Son and Kim are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Son with the specified features of Kim because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Son to have the active structure being hollow structures; the active structures comprising channel layers, and first active layers and second active layers located on opposite sides of the channel layers in a third direction, the third direction is parallel to the top surface of the substrate; the transistor structures further comprising: insulating filling layers, the active structures being distributed around peripheries of the insulating filling layers; wherein a thickness of the insulating filling layers is greater than or equal to a thickness of the channel layers in the first direction, as taught by Kim, for the purpose of improving control of gate for channel.
Regarding claim 17, Son in view of Kim discloses the semiconductor structure according to claim 14 as described above.
Son further discloses, in at least figures 4, 7-8C, and related text, a material of the gate layers (GE, [42]) is titanium nitride ([42]) and a material of the interlayer insulating layers (IL1, [58]) is a nitride material ([58]).
Son does not explicitly disclose a material of the word line is metal molybdenum.
Kim teaches, in at least figures 9A, 9B, and related text, the device comprising a material of the word line ([46]) is metal molybdenum ([46]), for the purpose of providing low-resistance conductive material ([46]).
Son and Kim are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Son with the specified features of Kim because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Son to have the material of the word line is metal molybdenum, as taught by Kim, for the purpose of providing low-resistance conductive material ([46], Kim).
Regarding claim 18, Son in view of Kim discloses the semiconductor structure according to claim 16 as described above.
Son further discloses, in at least figures 4, 7-8C, and related text, the memory units (SP/GI/GE/DS, [33], [97]) further comprise capacitor structures (DS, [73]) located outside the transistor structures (SP/GI/GE, [97]) in the third direction (D2, figures).
Son does not explicitly disclose the capacitor structures comprise: lower electrode layers comprising main body portions and extension portions connected to the main body portions in the third direction, the extension portions covering top surfaces of the second active layers and bottom surfaces of the second active layers, the main body portions covering sidewalls of the second active layers, and the top surfaces of the second active layers and the bottom surfaces of the second active layers being distributed at opposite ends of the second active layers in the first direction; dielectric layers covering surfaces of the lower electrode layers; upper electrode layers covering surfaces of the dielectric layers.
Kim teaches, in at least figures 9A, 9B, and related text, the device comprising the capacitor structures (CAP, [32]) comprise: lower electrode layers (SN, [33]) comprising main body portions and extension portions connected to the main body portions in the third direction (D2, figures), the extension portions covering top surfaces of the second active layers (SD2, [32]) and bottom surfaces of the second active layers (SD2, [32]), the main body portions covering sidewalls of the second active layers (SD2, [32]), and the top surfaces of the second active layers (SD2, [32]) and the bottom surfaces of the second active layers (SD2, [32]) being distributed at opposite ends of the second active layers (SD2, [32]) in the first direction (D1, figures); dielectric layers (DE, [33]) covering surfaces of the lower electrode layers (SN, [33]); upper electrode layers (PN, [33]) covering surfaces of the dielectric layers (DE, [33]), for the purpose of reducing contact resistance.
Son and Kim are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Son with the specified features of Kim because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Son to have the capacitor structures comprising: lower electrode layers comprising main body portions and extension portions connected to the main body portions in the third direction, the extension portions covering top surfaces of the second active layers and bottom surfaces of the second active layers, the main body portions covering sidewalls of the second active layers, and the top surfaces of the second active layers and the bottom surfaces of the second active layers being distributed at opposite ends of the second active layers in the first direction; dielectric layers covering surfaces of the lower electrode layers; upper electrode layers covering surfaces of the dielectric layers, as taught by Kim, for the purpose of reducing contact resistance.
Regarding claim 20, Son in view of Kim discloses the semiconductor structure according to claim 14 as described above.
Son does not explicitly disclose a material of the active structures is an oxide semiconductor material.
Kim teaches, in at least figures 9A, 9B, and related text, the device comprising a material of the active structures (ACT, [45]) is an oxide semiconductor material ([45]), for the purpose of improving mobility of electron thereby improving operation speed of device.
Son and Kim are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Son with the specified features of Kim because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Son to have the material of the active structures being an oxide semiconductor material, as taught by Kim, for the purpose of improving mobility of electron thereby improving operation speed of device.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son (US 2021/0183862) in view of Kim (US 2022/0005809), and further in view of Lee (US 2022/0130834).
Regarding claim 3, Son in view of Kim discloses the method for forming a semiconductor structure according to claim 2 as described above.
Son further discloses, in at least figures 4, 7-21, and related text, a material of the first sacrifice layers (IL2, [84]) and a material of the third sacrifice layers (IL2, [84]) each are an oxide material ([84]), and a material of the second sacrifice layers (SL, [84]) is a silicon material ([84]).
Son in view of Kim does not explicitly disclose a material of the second sacrifice layers is a polysilicon material.
Lee teaches, in at least figure 4 and related text, the method comprising a material of the second sacrifice layers (432-1/…/432-N, [52]) is a polysilicon material ([52]), for the purpose of providing gate all around (GAA) structure at the channel region of the semiconductor material for better electrostatic control on the channel, better subthreshold slope and a more cost effective process ([22]).
Son, Kim, and Lee are analogous art because they all are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Son in view of Kim with the specified features of Lee because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Son in view of Kim to have the material of the second sacrifice layers being a polysilicon material, as taught by Lee, for the purpose of providing gate all around (GAA) structure at the channel region of the semiconductor material for better electrostatic control on the channel, better subthreshold slope and a more cost effective process ([22], Lee).
Allowable Subject Matter
Claims 5-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 5 that recite "removing the second sacrifice layers in the transistor regions along the bit line trenches to form the first trenches located between the first sacrifice layers and the third sacrifice layers in the transistor regions" in combination with other elements of the base claims 1 and 5.
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 14 and 19 that recite "a thickness of the word line located on top surfaces of the gate layers or on bottom surfaces of the gate layers is greater than or equal to a thickness of the gate layers in the first direction" in combination with other elements of the base claims 14 and 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811