DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Restriction to one of the following inventions is required under 35 U.S.C. 121:
I. Claims 1-17, drawn to a semiconductor structure and chip, classified in H10D30/6735.
II. Claims 18-20, drawn to a method of forming a semiconductor structure, classified in H10D84/0135.
The inventions are independent or distinct, each from the other because:
Inventions I and II are related as process of making and product made. The inventions are distinct if either or both of the following can be shown: (1) that the process as claimed can be used to make another and materially different product or (2) that the product as claimed can be made by another and materially different process (MPEP § 806.05(f)). In the instant case the product as claimed can be made by another and materially different process, for example, the gate structures in claims 1 and 9 can be made by depositing the permanent metal gate material instead of using a dummy gate, removing the dummy gate and forming a metal gate as recited in claim 18.
Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
the inventions have acquired a separate status in the art in view of their different classification and their divergent subject matter and the inventions require a different field of search including searching different classes/subclasses and employing different search strategies or search queries. Applicant is advised that the reply to this requirement to be complete must include (i) an election of an invention to be examined even though the requirement may be traversed (37 CFR 1.143) and (ii) identification of the claims encompassing the elected invention.
The election of an invention may be made with or without traverse. To reserve a right to petition, the election must be made with traverse. If the reply does not distinctly and specifically point out supposed errors in the restriction requirement, the election shall be treated as an election without traverse. Traversal must be presented at the time of election in order to be considered timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are added after the election, applicant must indicate which of these claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
During a telephone conversation with attorney Michelle Lecointe (reg. no. 46,8610 on Friday, February 20, 2026, provisional election was made without traverse to prosecute the invention of the semiconductor structure and chip, claims 1-17. Affirmation of this election must be made by applicant in replying to this Office action. Claims 18-20 are withdrawn from further consideration by the examiner, 37 CFR 1.142(b), as being drawn to a non-elected invention.
The examiner has required restriction between product or apparatus claims and process claims. Where applicant elects claims directed to the product/apparatus, and all product/apparatus claims are subsequently found allowable, withdrawn process claims that include all the limitations of the allowable product/apparatus claims should be considered for rejoinder. All claims directed to a nonelected process invention must include all the limitations of an allowable product/apparatus claim for that process invention to be rejoined.
In the event of rejoinder, the requirement for restriction between the product/apparatus claims and the rejoined process claims will be withdrawn, and the rejoined process claims will be fully examined for patentability in accordance with 37 CFR 1.104. Thus, to be allowable, the rejoined claims must meet all criteria for patentability including the requirements of 35 U.S.C. 101, 102, 103 and 112. Until all claims to the elected product/apparatus are found allowable, an otherwise proper restriction requirement between product/apparatus claims and process claims may be maintained. Withdrawn process claims that are not commensurate in scope with an allowable product/apparatus claim will not be rejoined. See MPEP § 821.04. Additionally, in order for rejoinder to occur, applicant is advised that the process claims should be amended during prosecution to require the limitations of the product/apparatus claims. Failure to do so may result in no rejoinder. Further, note that the prohibition against double patenting rejections of 35 U.S.C. 121 does not apply where the restriction requirement is withdrawn by the examiner before the patent issues. See MPEP § 804.01.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/21/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract and title are consistent with the requirements set forth in the MPEP 608.01(b) and 606, respectively.
Claim Objections
Claim 8 is objected to because of the following informalities: line 2 recites “the first dielectric” which is actually “the first gate dielectric.” Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chu et al. US PGPub. 2022/0375936. Regarding claim 1, Chu teaches a semiconductor structure (200, fig. 10A) [0016] comprising: a first gate-all-around field effect transistor (200A, fig. 10A) [0010], [0016], the first gate-all-around field effect transistor (200A) including: an upper nanosheet (topmost 215, fig. 10A) [0016]; and a first gate structure (280+282+430+350, fig. 10A); wherein the first gate structure (280+282+430+350) is laterally confined by first gate spacers (247, fig. 10A) [0022] and surrounds the upper nanosheet (215, fig. 10A-B); wherein the first gate structure (280+282+430+350) comprises a first gate dielectric (280, fig. 10A) [0025] on the upper nanosheet (215) and a u-shaped first high-k material (282, fig. 10A) [0025] on a lower portion of the first gate spacers (247) and on the first gate dielectric (280) (Chu et al., fig. 10A). Regarding claim 2, Chu teaches the semiconductor structure of claim 1, wherein the first gate structure (282+280+430+350) further comprises: a u-shaped first work function material (430, fig. 10A) [0038] in (indirect) contact with an upper portion of the first gate spacers (247) and in (direct) contact with the first high-k material (282); and a first metal gate fill (350, fig. 10A) [0046] in (direct) contact with the first work function material (430) (Chu et al., fig. 10A). Regarding claim 3, Chu teaches the semiconductor structure of claim 2, wherein the first metal gate fill (350) has a top dimension and a bottom dimension (top and bottom dimensions being the same)(Chu et al., fig. 10A).
Claims 1 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jhan et al. US PGPub. 2022/0059678. Regarding claim 1, Jhan teaches a semiconductor structure (fig. 25D-E) [0071] comprising: a first gate-all-around field effect transistor (fig. 25D) [0010], the first gate-all-around field effect transistor (fig. 25D) including: an upper nanosheet (16, fig. 17D and 25D )[0069]; and a first gate structure (66+68+70, fig. 25D); wherein the first gate structure (66+68+70) is laterally confined by first gate spacers (54, fig. 25D) [0046] and surrounds the upper nanosheet (16); wherein the first gate structure (66+68+70) comprises a first gate dielectric (66, fig. 25d) [0069] on the upper nanosheet (16) and a u-shaped first high-k material (68, fig. 25D) [0071] on a lower portion of the first gate spacers (54) and on the first gate dielectric (66) (Jhan et al., fig. 25D). Regarding claim 5, Jhan teaches the semiconductor structure of claim 1, wherein the first gate dielectric (66) is in (indirect) contact with the entire height of the gate spacer (54) and is sandwiched by the gate spacer (54) and first high-k material (68) on the lower portion of the first gate spacers (54) (Jhan et al., fig. 25D).
Claims 9-10 and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Song US PGPub. 2021/0358924.
Regarding claim 9, Song teaches a semiconductor chip (1030, fig. 19) [0198] comprising: a first transistor (I, fig. 12 and 16) [0199], including: a first gate trench (140t, fig. 12) [0044] having a bottom and sidewalls; a first upper nanosheet (UAP1, fig. 12, 14 and 16; the gate stack cross-section of fig. 16 will be similar to the top portion of fig. 1) [0152] defining the bottom of the first gate trench (140t); a first pair of gate spacers (140, fig. 12) [0040] above the first upper nanosheet (UAP1) defining a portion of the sidewalls of the first gate trench (140t), wherein the first pair of gate spacers (140) has a lower portion and an upper portion; a first gate dielectric (135, fig. 12; made of SiO2 [0053], [0080]) on the first upper nanosheet (UAP2); and a first u-shaped high-k material (130, fig. 12; portion 132 of 130 is made of HfO2 which is a well-known hi-k dielectric in the art) [0071] on the first gate dielectric (135) and on the lower portion of the first pair of gate spacers (140); and a second transistor (II, fig. 12 and 16) [0199] including: a second gate trench (240t, fig. 12) [0044] having a bottom and sidewalls; a second upper nanosheet (UAP2, fig. 12, 14 and 16; the gate stack cross-section of fig. 16 will be similar to the top portion of fig. 1) [0152] defining the bottom of the gate trench (240t); a second pair of gate spacers (240, fig. 12) [0040] above the second upper nanosheet (UAP2) defining a portion of the sidewalls of the second gate trench (240t); a second gate dielectric (235, fig. 12; made of SiO2 [0063], [0080]) on the second upper nanosheet (UAP2); and a second u-shaped high-k material (230, fig. 12; portion 232 of 230 is made of HfO2 which is a well-known hi-k dielectric in the art) [0071] on the second gate dielectric (235) and on the sidewalls of the second pair of gate spacers (240) (Song, fig. 12 and 16). Regarding claim 10, Song teaches the semiconductor structure of claim 9, wherein each of the first (135) and second gate dielectrics (235) have a thickness (t3 and t4, fig. 12); and wherein the thickness (t3, fig. 12) of the first gate dielectric (135) is greater [0085] than the thickness (t4, fig. 12) of the second gate dielectric (235) 9Song, fig. 12, [0085]).
Regarding claim 12, Song teaches the semiconductor structure of claim 10 wherein the first (135) and second gate dielectrics (235) include one or more of silicon nitride and a silicon oxide (135 and 235 are made of the same material of 132 and 232 which is SiO2, [0053], [0063] [0080]) (Song, [0053],[0063] [0080]).
Regarding claim 13, Song teaches the semiconductor structure of claim 10 wherein the first (130) and second high-k materials (230) are the same materials (131 of 130 and 232 of 230 are made of HfO, [0071]) with the same thicknesses (fig. 7, [0117]) (Song, fig. 7).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chu et al. US PGPub. 2022/0375936 as applied to claim 3 above, and further in view of Song US PGPub. 2021/0358924. Regarding claim 4, Chu does not teach the semiconductor structure of claim 3, wherein the top dimension is greater than the bottom dimension. However, Song teaches a semiconductor structure/transistor (I, fig. 12 and 16) [0199] comprising a gate structure (GS1, fig. 12) [0028] comprising a first metal gate fill (120, fig. 12) [0045], wherein the first metal gate fill (120) has a top dimension and a bottom dimension, wherein the top dimension is greater than the bottom dimension (fig. 12) (Song, fig. 12). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the shape of the metal gate fill of Chu such that the top dimension is greater than the bottom dimension as taught by Song because such metal fill structure are well known in the art and such structure is art recognized and suitable for the intended purpose of improving the reliability of the transistor (Song, [0098]) (see MPEP 2144.07).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Song US PGPub. 2021/0358924 as applied to claim 10 above.
Regarding claim 11, Song teaches the semiconductor structure of claim 10 wherein the thickness (t3) of the first gate dielectric (135) is greater [0085] than the thickness (t4) of the second gate dielectric (235) but fails to teach wherein the thickness (t3) of the first gate dielectric (135) is one to three times the thickness (t4) of the second gate dielectric (235). However, at the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in art to use the thicknesses of the first and second gate dielectric layers in the range as claimed in order to decrease subthreshold swing of the transistor and improve reliability of the transistor (Song, [0098]), because it has been held that where the general conditions of the claims are discloses in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See MPEP 2144.05.
Allowable Subject Matter
Claims 6-8 and 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior arts of record taken alone or in combination neither anticipates nor renders obvious: a semiconductor structure comprising “an insulating metal gate cap located above the metal fill and work function metal, which is coplanar with the first gate dielectric” as recited in claim 6 in combination with the rest of the limitations of claims 1 and 5; a semiconductor structure comprising “an adjacent nanosheet below the upper nanosheet separated by a vertical distance, wherein the first gate dielectric is 20% to 80% of the vertical distance” as recited in claim 8 in combination with the rest of the limitation of claim 1; a semiconductor structure comprising “a top dielectric in contact with the upper nanosheet and below the first pair of gate spacers wherein the top dielectric further defines the sidewall of the gate trench; and wherein the first gate dielectric is laterally confined by the top dielectric and vertically confined by the upper nanosheet and the first high-k dielectric” as recited in claim 14 in combination with the rest of the limitations of claims 9-10; and a semiconductor structure comprising “a top dielectric in contact with the first upper nanosheet and below the pair of first gate spacers wherein the top dielectric further defines the sidewall of the gate trench; and wherein the first gate dielectric is u-shaped and is in contact with the upper nanosheet, the top dielectric and the first pair of gate spacers” as recited in claim 15 in combination with the rest of the limitations of claims 9-10.
Claims 7 and 16-17 are also objected to as allowable for further limiting and depending upon allowable claims 5 and 15.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen et al. US PGPub. 2025/0040200 and Hsiao et al. US PGPub. 2022/0367688 also teach gate-all-around transistor with u-shaped high-k material.
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892