DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/15/2023, 3/19/2024 and 8/2/2024 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The abstract is consistent with the requirements set forth in the MPEP 608.01(b). The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE COMPRISING DOPE MONOCRYSTALLINE SEMICONDUCTOR LAYER, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC SYSTEM INCLUDING THE SAME
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7-8, 12 and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang US PGPub. 2021/0375914. Regarding claim 1, Zhang teaches a semiconductor device (100, fig. 1) [0033], comprising: a gate stacking structure (116+118, fig. 1) including alternating gate electrodes (116, fig. 1) [0042] and insulation layers (118, fig. 1) [0041] on an insulation portion (ILD 134, fig. 1) [0053]; a channel structure (124, fig. 1) [0045] crossing the insulation portion (134) and extending through the gate stacking structure (116+118); and a horizontal conductive layer (120, fig. 1) [0047] connected [0046] to the channel structure (124) between the insulation portion (134) and the gate stacking structure (116+118), the horizontal conductive layer (120) including a doped monocrystalline semiconductor layer [0047] with a dopant (N-type, [0043]) (Zhang fig. 1).
Regarding claim 7, Zhang teaches the semiconductor device as claimed in claim 1, wherein: the doped monocrystalline semiconductor layer (120) is spaced apart (by 122, fig. 1) from the channel structure (124), and the horizontal conductive layer (120) further includes a doped polycrystalline semiconductor layer (122, fig. 1) [0047] connecting the doped monocrystalline semiconductor layer (120) and the channel structure (124) (Zhang, fig. 1). Regarding claim 8, Zhang teaches the semiconductor device as claimed in claim 7, wherein: the doped monocrystalline semiconductor layer (120) is continuous, except for an opening region (where 122, 129, 124 is located, fig. 1; hereinafter called 122’) in which the channel structure (124) is located, and the doped polycrystalline semiconductor layer (122) includes at least a (inner) portion connecting a side surface of the channel structure (124) and a side (outer portion) surface of the doped monocrystalline semiconductor layer (20) in a horizontal direction within the opening region (122’) (Zhang , fig. 1).
Regarding claim 12, Zhang teaches the semiconductor device as claimed in claim 7, wherein a thickness (thk-120; examiner’s fig. 1) of the doped monocrystalline semiconductor layer (20) is greater than a thickness (thk-122; examiner’s fig. 1) of the doped polycrystalline semiconductor layer (122) (Zhang, fig. 1).
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Examiner’s Fig. 1
Regarding claim 15, Zhang teaches the semiconductor device as claimed in claim 1, wherein the doped monocrystalline semiconductor layer (120) includes a doped monocrystalline silicon [0047] or a doped monocrystalline silicon-germanium (Zhang, fig. 1, [0047]). Regarding claim 16, Zhang teaches the semiconductor device as claimed in claim 1, further comprising: a cell region (104, fig. 1) [0041] including the gate stacking structure (116+118), the channel structure (124), and the horizontal conductive layer (120); and a bonding structure (110+112, fig. 1) [0037] bonding the cell region (104) to a circuit region (102/108, fig. 1) [0034] (Zhang, fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang US PGPub. 2021/0375914 as applied to claim 1 above, and further in view of Zhang et al. US Pat. 10,879,269 (hereinafter called Zhang ‘269). Regarding claim 13, Zhang does not teach the semiconductor device as claimed in claim 1, wherein a thickness of the doped monocrystalline semiconductor layer (120) is 10 nm to 1 μm. However, Zhang ‘269 teaches a semiconductor device (fig. 46A) wherein a thickness of the doped monocrystalline semiconductor layer (6, fig. 46A) [col. 21/line 47] is 10 nm to 1 μm (50-500nm, [col. 21/line 56]) (Zhang ‘269 et al., [col. 21/line 56]). Accordingly, at the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in art to combine the teaching of Zhang with that of Zhang ‘269 such that the thickness of the doped monocrystalline semiconductor is in the range as claimed because Zhang ‘269 discloses that even lesser or greater thicknesses can be used (Zhang ‘269, [col. 21/lines 56-57]) and it has been held that where the general conditions of the claims are disclosed in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See MPEP 2144.05. Regarding claim 14, Zhang does not teach the semiconductor device as claimed in claim 1, wherein a thickness of the doped monocrystalline semiconductor layer (120) is greater than a thickness of each of the insulation layers (118) and the gate electrodes (116).
However, Zhang ‘269 teaches a semiconductor device (fig. 46A) wherein a thickness (50-500nm, [col. 21/line 56]) of the doped monocrystalline semiconductor layer (6, fig. 46A) [col. 21/line 47] is greater than a thickness (20-400nm, [col. 22/lines 8-9 and 24]) of each of the insulation layers (32, fig. 46A) [col. 22/line 5] and the gate electrodes (42, fig. 46A) [col. 22/line 11] (Zhang ‘269 et al., [col. 22/lines 8-9 and 24]). Accordingly, at the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in art to combine the teaching of Zhang with that of Zhang ‘269 such that the thickness of the doped monocrystalline semiconductor, the insulating layers and the gate electrode layers are in the range as claimed because Zhang ‘269 discloses that even lesser or greater thicknesses can be used (Zhang ‘269, [col. 22/lines 8-9 and 24-25]) and it has been held that where the general conditions of the claims are disclosed in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See MPEP 2144.05. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yamasaki et al. US PGPub. 2025/0380432 in view of Zhang US PGPub. 2021/0375914. Regarding claim 20, Yamasaki teaches an electronic system (1003, fig. 1) [0049], comprising: a main substrate (1003, fig. 4) [0049]; a semiconductor device (1, fig. 1) [0048] on the main substrate (1003); and a controller (1002, fig. 1) [0049] electrically connected to the semiconductor device (1) on the main substrate (1003) (Yamasaki et al., fig. 1). But Yamasaki fails to teach wherein the semiconductor device (1) includes: a gate stacking structure having alternating gate electrodes and insulation layers on an insulation portion, a channel structure crossing the insulation portion and extending through the gate stacking structure, and a horizontal conductive layer connected to the channel structure between the insulation portion and the gate stacking structure, the horizontal conductive layer including a doped monocrystalline semiconductor layer with a dopant. However, Zhang teaches a semiconductor device (100, fig. 1) [0033] including: a gate stacking structure (116+118, fig. 1) having alternating gate electrodes (116, fig. 1) [0042] and insulation layers (118, fig. 1) [0041] on an insulation portion (ILD 134, fig. 1) [0053]; a channel structure (124, fig. 1) [0045] crossing the insulation portion (134) and extending through the gate stacking structure (116+118); and a horizontal conductive layer (120, fig. 1) [0047] connected [0046] to the channel structure (124) between the insulation portion (134) and the gate stacking structure (116+118), the horizontal conductive layer (120) including a doped monocrystalline semiconductor layer [0047] with a dopant (N-type, [0043]) (Zhang fig. 1).
At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to make a simple substitution of the semiconductor device of Yamasaki with the semiconductor device of Zhang because the semiconductor device structure of Zhang is well known in the art and such structure is art recognized and suitable for the intended purpose having a semiconductor device with improved device performance including avoiding leakage current and parasitic capacitance (Zhang, [0030]) (see MPEP 2144.07).
Allowable Subject Matter
Claims 2-6 and 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a semiconductor device wherein “the doped monocrystalline semiconductor layer has a P-type region and an N-type region, the P-type region and the N-type region defining a pn junction” as recited in claim 2 in combination with the rest of the limitations of claim 1; a semiconductor device “the doped monocrystalline semiconductor layer includes a first conductivity type region and a second conductivity type region having a conductivity type opposite to a conductivity type of the first conductivity type region, and the semiconductor device further comprises a first contact portion electrically connected to the first conductivity type region through the insulation portion and a second contact portion electrically connected to the second conductivity type region through the insulation portion” as recited in claim 3 in combination with the rest of the limitations of claim 1; a semiconductor device wherein “the channel structure includes a protruded portion protruding above the gate stacking structure at a portion adjacent to the insulation portion, and the protruded portion includes a doped channel layer having a same conductivity type as the doped polycrystalline semiconductor layer” as recited in claim 9 in combination with the rest of the limitations of claims 1 and 7;
a semiconductor device wherein “the doped polycrystalline semiconductor layer has a first conductivity type, the doped monocrystalline semiconductor layer includes a horizontal portion and a connection portion, the horizontal portion is adjacent to an outer surface of the gate stacking structure and is composed of a region having the first conductivity type, and the connection portion is connected to the horizontal portion and is composed of a region having a second conductivity type opposite to the first conductivity type” as recited in claim 10 in combination with the rest of the limitations of claims 1 and 7; and
a semiconductor device wherein “the doped polycrystalline semiconductor layer has a second conductivity type, the doped monocrystalline semiconductor layer includes a horizontal portion and a connection portion, the horizontal portion includes a first region and a second region, the first region being adjacent to an outer surface of the gate stacking structure and having a first conductivity type opposite to the second conductivity type, and the second region having the second conductivity type at a surface of the first region, and the connection portion is connected to the horizontal portion and is composed of a region having the second conductivity type” as recited in claim 11 in combination with the rest of the limitations of claims 1 and 7.
Claims 4-6 are also objected to as allowable for further limiting and depending upon allowable claims 3. Claims 17-19 are allowed.
The following is an examiner’s statement of reasons for allowance: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a manufacturing method of a semiconductor device comprising “forming an opening penetrating the stacking structure to expose a part of the first doped monocrystalline semiconductor layer, such that a first part of the first doped monocrystalline semiconductor layer is not exposed and a second part of first doped monocrystalline semiconductor layer is exposed; doping a second conductivity type dopant to the second part of the first doped monocrystalline semiconductor, such that the first part of the first doped monocrystalline semiconductor layer is a first conductivity type region and the second part of the first doped monocrystalline semiconductor layer is a second conductivity type region” and “forming a doped polycrystalline semiconductor layer on the doped monocrystalline semiconductor layer” as recited in claim 17.
Claims 18-19 are also allowed for further limiting and depending upon allowed claim 17. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Oh et al. US PGPub. 2022/0359564 teaches a semiconductor device comprising a horizontal doped semiconductor layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NDUKA E OJEH whose telephone number is (571)270-0291. The examiner can normally be reached M-F; 9am - 5pm..
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892
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