DETAILED ACTION
Status of the Application
1. Claims 1 – 20 are pending and are under examination in this action.
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Requirement for Necessary Information
3. The Examiner has become aware of a plethora of documents that may be material to patentability but have not been included in any IDS submissions even though the Applicant has been aware of these references for a substantial amount of time.
37 CFR 1.56(a) requires that “[e]ach individual associated with the filing and prosecution of a patent application has a duty of candor and good faith in dealing with the Office, which includes a duty to disclose to the Office all information known to that individual to be material to patentability”.
Specifically, Applicant has failed to disclose the existence of any of the following co-pending applications: 18/080,891, 17/949,358, 18/092,509, 17/898,187, 17/879,514, 18/077,457, 18/058,725, 17/836,609, 17/689,440, 17/339,271, 17/243,544.
Applicant has also failed to disclose the existence of issued U.S. Patent No. 11,711,951.
Each of these co-pending applications and issued patent may be material to the patentability of this application for prior art and double patenting purposes and thus constitute necessary information that must be submitted to the Office.
Additionally, the references cited in these co-pending applications and issued patent may also be material to the patentability of this application for prior art purposes and thus constitute necessary information that must be submitted to the Office.
4. Required Information: 37 CFR 1.105(a)(1)(viii) – In light of the above findings by the Examiner, Applicant is required to submit a list of every reference of which they are aware that may be material to the patentability of the claimed invention, as defined by 37 CFR 1.56(b). This requirement is being made in view of 37 CFR 1.56 and 1.105 in order to ensure that the most relevant prior art is fully considered.
Failure to provide a detailed list of all information that may be material to patentability of the claimed invention as defined by 37 CFR 1.56(b) will be considered non-responsive.
Accordingly, each piece of information referred to above is necessary material that is required to be submitted in order to properly proceed with the examination of this Application.
Applicant should review their patent portfolio for any other co-pending applications, issued patents, and associated references that may be material to patentability when responding to this requirement.
Claim Rejections - 35 USC § 112(b)
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
6. Claim 10 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claim 10, the recitation of “the first and second auxiliary electrodes” lack sufficient antecedent basis. Accordingly, this claim is indefinite.
Claim Rejections - 35 USC § 102
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
8. Claims 1 – 2, 4, 6 – 17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (U.S. Pub. 2021/0376045).
Regarding claim 1, Lee teaches: a display device (FIG. 1; paragraph [0059]; display device 10), comprising:
a first voltage line disposed in a first metal layer on a substrate and that provides a high-level voltage (FIGS. 4, 8; paragraphs [0077], [0078], [0091], [0117], [0125]; VDL_V [first voltage line] is a vertical portion of first voltage wiring VDL which a first power supply [high-level] voltage. The layer of conductive components between buffer layer BF and substrate SUB is a “first metal layer”);
a vertical voltage line disposed on a side of the first voltage line and that provides a low-level voltage (FIGS. 4, 8; paragraphs [0077], [0091]; VSL_V [vertical voltage line] is a vertical portion of second voltage wiring VSL which provides a second power supply [low-level] voltage. VSL_V is disposed to the left, and therefore on a side of, VDL_V);
a first transistor disposed in an active layer on the first metal layer (FIGS. 3, 8; paragraph [0119], [0125]; first transistor T1 is disposed in an “active layer”, because it is where active layers ACT1 of the first transistors T1 are located. The “active layer” is the layer of conductive components between buffer layer BF and gate insulating layer GI and is on the “first metal layer”) and including:
a drain electrode electrically connected to the first voltage line (FIGS. 3, 8; paragraphs [0119], [0136]; drain region [electrode] D1 is electrically connected to VDL_V [first voltage line] via first conductive pattern DP1);
an active region adjacent to the drain electrode (FIGS. 3, 8; paragraph [0119]; first active layer [region] ACT1 is adjacent to drain region [electrode] D1);
a source electrode adjacent to the active region (FIGS. 3, 8; paragraph [0119]; source region [electrode] S1 is adjacent to first active layer [region] ACT1); and
a gate electrode disposed in a second metal layer on the active layer (FIGS. 3, 8; paragraphs [0127], [0134]; gate electrode G1 is disposed on the “active layer” in a “second metal layer” that is the layer of conductive components between gate insulating layer GI and first interlayer insulating layer IL1);
a first anode connection electrode disposed in a third metal layer on the second metal layer and electrically connected to the source electrode of the first transistor (FIGS. 8, 11; paragraphs [0119], [0132], [0142]; second capacitive [first anode] electrode CSE2 is electrically connected to source region [electrode] S1 of transistor T1. CSE2 is disposed on the “second metal layer” in a “third metal layer” that is the layer of conductive components between first layer insulating layer IL1 and second interlayer insulating layer IL2);
a first electrode and a second electrode that are disposed in a fourth metal layer on the third metal layer and extended in a first direction (FIGS. 8, 12; paragraphs [0135], [0145]; first electrode RME1 and second electrode RME2 extend in direction DR2. Electrodes RME1 and RME2 are disposed on the “third metal layer” in a “fourth metal layer” that is the layer of conductive components between second interlayer insulating layer IL2 and insulating layer PAS1); and
a plurality of light-emitting element areas including a plurality of light-emitting elements aligned between the first and second electrodes and spaced apart from the first voltage line and the vertical voltage line in a plan view (FIGS. 3, 12; paragraphs [0108], [0149]; a plurality of light emitting elements [area] ED include a light emitting diode [element] EL that is aligned between first electrode RME1 and second electrode RME2. Elements [area] ED and diodes [elements] EL are spaced apart from VDL_V [first voltage line] and VSL_V [second voltage line], as illustrated).
Regarding claim 2, Lee teaches: further comprising: an initialization voltage line disposed between the first voltage line and the vertical voltage line in the first metal layer (FIGS. 4. 8; paragraphs [0091]; initialization voltage wiring VIL is disposed between VDL_V [first voltage line] and VSL_V [second voltage line], as illustrated. Initialization voltage wiring VIL is disposed in the “first metal layer”, which is the layer of conductive components between buffer layer BF and substrate SUB),
wherein the plurality of light-emitting elements overlaps the initialization voltage line (FIGS. 4, 7, 8; the light emitting diodes [elements] EL overlap the initialization voltage wiring VIL).
Regarding claim 4, Lee teaches: further comprising: a data line disposed in the first metal layer and that provides a data voltage (FIGS. 3, 9; paragraph [0094], [0116]; data line DTL1 provides data signals [voltages], and is disposed in the “first metal layer”, which is the layer of conductive components between buffer layer BF and substrate SUB);
a second transistor that provides the data voltage to the gate electrode of the first transistor (FIG. 3; paragraph [0079]; second transistor T2 provides the data signal [voltage] from data line DTL to the gate electrode [region G1] of first transistor T1);
a third transistor electrically connecting the initialization voltage line with the source electrode of the first transistor (FIG. 3; paragraph [0080]; third transistor T3 electrically connects initialization voltage wiring VIL with a source electrode [region S1] of first transistor T1); and
a first capacitor (FIG. 3; paragraph [0093]; storage capacitor Cst) including:
a first capacitor electrode electrically connected to the gate electrode of the first transistor (FIG. 3; storage capacitor Cst includes an upper [first] electrode that is electrically connected to the gate electrode [region G1] of first transistor T1); and
a second capacitor electrode electrically connected to the source electrode of the first transistor (FIG. 3; storage capacitor Cst includes a lower [second] electrode that is electrically connected to the source electrode [region S1] of first transistor T1).
Regarding claim 6, Lee teaches: further comprising: a first auxiliary electrode disposed in the second metal layer, overlapping the first voltage line, and electrically connected to the first voltage line (FIGS. 8, 11; paragraph [0136]; the portion of first conductive pattern DP1 that is disposed through gate insulating layer GI via contact hole CT1 is interpreted as the “first auxiliary electrode”. This “first auxiliary electrode” portion of DP1 is disposed in the “second metal layer”, overlaps VDL_V [first voltage line], and is electrically connected to VDL_V [first voltage line]); and
a second auxiliary electrode disposed in the third metal layer, overlapping the first voltage line, and electrically connected to the first voltage line (FIGS. 8, 11; paragraph [0136]; the portion of first conductive pattern DP1 that is disposed on first interlayer insulating layer IL1 is interpreted as the “second auxiliary electrode”. This “second auxiliary electrode” portion of DP1 is disposed in the “third metal layer”, overlaps VDL_V [first voltage line], and is electrically connected to VDL_V [first voltage line]).
Regarding claim 7, Lee teaches: wherein the light-emitting element areas are spaced apart from the first and second auxiliary electrodes in a plan view (FIGS. 8. 9; light emitting elements [area] ED do not overlap, and are therefore spaced apart from, the “first auxiliary electrode” and “second auxiliary electrode” portions of first conductive pattern DP1).
Regarding claim 8, Lee teaches: wherein the second auxiliary electrode electrically connects the first voltage line with the drain electrode of the first transistor (FIGS. 8, 11; paragraph [0136]; the “second auxiliary electrode” portion of first conductive pattern DP1 electrically connected VDL_V [first voltage line] to drain region [electrode] D1 of first transistor T1).
Regarding claim 9, Lee teaches: further comprising: a third auxiliary electrode disposed in the second metal layer, overlapping the vertical voltage line, and electrically connected to the vertical voltage line (FIGS. 8, 11; paragraph [0140]; the portion of fifth conductive pattern DP5 that is disposed through gate insulating layer GI via contact hole CT9 is interpreted as the “third auxiliary electrode”. This “third auxiliary electrode” portion of DP5 is disposed in the “second metal layer”, overlaps VSL_V [vertical voltage line], and is electrically connected to VSL_V [vertical voltage line]); and
a fourth auxiliary electrode disposed in the third metal layer, overlapping the vertical voltage line, and electrically connected to the vertical voltage line (FIGS. 8, 11; paragraph [0140]; the portion of fifth conductive pattern DP5 that is disposed on first interlayer insulating layer IL1 is interpreted as the “fourth auxiliary electrode”. This “fourth auxiliary electrode” portion of DP5 is disposed in the “third metal layer”, overlaps VSL_V [vertical voltage line], and is electrically connected to VSL_V [vertical voltage line]).
Regarding claim 10, Lee teaches: wherein the light-emitting element areas are spaced apart from the first and second auxiliary electrodes in a plan view (FIGS. 8. 9; light emitting elements [area] ED do not overlap, and are therefore spaced apart from, the “third auxiliary electrode” and “fourth auxiliary electrode” portions of fifth conductive pattern DP5).
Regarding claim 11, Lee teaches: further comprising: a horizontal voltage line disposed in the third metal layer and electrically connected to the first voltage line (FIG. 11; paragraphs [0113], [0132]; horizontal [voltage line] portion VDL_H is disposed in the “third metal layer” and is electrically connected to VDL_V [first voltage line]); and
a second voltage line disposed in the third metal layer and electrically connected to the vertical voltage line (FIG. 11; paragraphs [0113], [0132]; horizontal portion VSL_H [second voltage line] is disposed in the “third metal layer” and is electrically connected to VSL_V [vertical voltage line]).
Regarding claim 12, Lee teaches: wherein the first electrode is electrically connected to the horizontal voltage line and receives the high-level voltage (FIG. 11; paragraph [0154]; the first electrode REM1 is electrically connected to the horizontal [voltage line] portion VDL_H via electrode line RM1 and VDL_V [first voltage line]. Due to this connection, first electrode REM1 receives the first power supply [high-level] voltage), and
the second electrode is electrically connected to the second voltage line and receives the low-level voltage (FIG. 11; paragraph [0154]; the second electrode REM2 is electrically connected to the horizontal portion VSL_H [second voltage line] via electrode line RM2 and VSL_V [vertical voltage line]. Due to this connection, second electrode REM2 receives the second power supply [low-level] voltage).
Regarding claim 13, Lee teaches: further comprising: a first contact electrode disposed in a fifth metal layer on the fourth metal layer and electrically connected to an end of each of the light-emitting elements (FIG. 8; paragraphs [0145], [0168]; first contact electrode CNE1 is disposed in on the “fourth metal layer” in a “fifth metal layer” that is the layer of conductive components disposed on first insulating layer PAS1. First contact electrode CNE1 is electrically connected to the right end of light emitting diodes [element] EL of light emitting elements [area] ED); and
a second contact electrode disposed in the fifth metal layer and electrically connected between an opposite end of each of the light-emitting elements and a second voltage line (FIG. 8; paragraphs [0077], [0140], [0145], [0168]; second contact electrode CNE2 is disposed in the “fifth metal layer” and is connected to between the opposite [left] end of light emitting diodes [element] EL of light emitting elements [area] ED and second electrode [voltage] line RM2 via second electrodes RME2).
Regarding claim 14, Lee teaches: a display device (FIG. 1; paragraph [0059]; display device 10), comprising:
a first voltage line disposed in a first metal layer on a substrate and that provides a high-level voltage (FIGS. 4, 8; paragraphs [0077], [0078], [0091], [0117], [0125]; VDL_V [first voltage line] is a vertical portion of first voltage wiring VDL which a first power supply [high-level] voltage. The layer of conductive components between buffer layer BF and substrate SUB is a “first metal layer”);
an initialization voltage line disposed on a side of the first voltage line and that provides an initialization voltage (FIGS. 4. 8; paragraphs [0091], [0095]; initialization voltage wiring VIL is disposed on a left side of VDL_V [first voltage line], as illustrated, and provides an initialization voltage);
a vertical voltage line disposed on a side of the first voltage line and that provides a low-level voltage (FIGS. 4, 8; paragraphs [0077], [0091]; VSL_V [vertical voltage line] is a vertical portion of second voltage wiring VSL which provides a second power supply [low-level] voltage. VSL_V is disposed to the left, and therefore on a side of, VDL_V);
a data line disposed in the first metal layer (FIGS. 3, 9; paragraph [0094], [0116]; data line DTL1 is disposed in the “first metal layer”, which is the layer of conductive components between buffer layer BF and substrate SUB);
a first transistor disposed in an active layer on the first metal layer (FIGS. 3, 8; paragraph [0119], [0125]; first transistor T1 is disposed in an “active layer”, because it is where active layers ACT1 of the first transistors T1 are located. The “active layer” is the layer of conductive components between buffer layer BF and gate insulating layer GI and is on the “first metal layer”) and including:
a drain electrode electrically connected to the first voltage line (FIGS. 3, 8; paragraphs [0119], [0136]; drain region [electrode] D1 is electrically connected to VDL_V [first voltage line] via first conductive pattern DP1);
an active region adjacent to the drain electrode (FIGS. 3, 8; paragraph [0119]; first active layer [region] ACT1 is adjacent to drain region [electrode] D1);
a source electrode adjacent to the active region (FIGS. 3, 8; paragraph [0119]; source region [electrode] S1 is adjacent to first active layer [region] ACT1); and
a gate electrode disposed in a second metal layer on the active layer (FIGS. 3, 8; paragraphs [0127], [0134]; gate electrode G1 is disposed on the “active layer” in a “second metal layer” that is the layer of conductive components between gate insulating layer GI and first interlayer insulating layer IL1);
a connection electrode disposed in a third metal layer on the second metal layer, electrically connected to the initialization voltage line and extended to a side of the data line (FIGS. 5. 8, 9; paragraphs [0114]; fourth conductive pattern DP4 [connection electrode] is disposed on the “second metal layer” in a “third metal layer” that is the layer of conductive components between first layer insulating layer IL1 and second interlayer insulating layer IL2. Fourth conductive pattern DP4 is electrically connected to initialization voltage wiring VIL and has a horizontal extent to the left side of data lines DL1);
a first electrode and a second electrode that are disposed in a fourth metal layer on the third metal layer and extended in a first direction (FIGS. 8, 12; paragraphs [0135], [0145]; first electrode RME1 and second electrode RME2 extend in direction DR2. Electrodes RME1 and RME2 are disposed on the “third metal layer” in a “fourth metal layer” that is the layer of conductive components between second interlayer insulating layer IL2 and insulating layer PAS1); and
a plurality of light-emitting element areas including a plurality of light-emitting elements aligned between the first and second electrodes and spaced apart from the first voltage line and the vertical voltage line in a plan view (FIGS. 3, 12; paragraphs [0108], [0149]; a plurality of light emitting elements [area] ED include a light emitting diode [element] EL that is aligned between first electrode RME1 and second electrode RME2. Elements [area] ED and diodes [elements] EL are spaced apart from VDL_V [first voltage line] and VSL_V [second voltage line], as illustrated).
Regarding claim 15, Lee teaches: wherein the plurality of light-emitting elements overlaps the initialization voltage line (FIGS. 4, 7, 8; the light emitting diodes [elements] EL overlap the initialization voltage wiring VIL).
Regarding claim 16, Lee teaches: further comprising: a second transistor that provides a data voltage to the gate electrode of the first transistor (FIG. 3; paragraph [0079]; second transistor T2 provides a data signal [voltage] from data line DTL to the gate electrode [region G1] of first transistor T1);
a third transistor electrically connecting the initialization voltage line with the source electrode of the first transistor (FIG. 3; paragraph [0080]; third transistor T3 electrically connects initialization voltage wiring VIL with a source electrode [region S1] of first transistor T1); and
a first capacitor (FIG. 3; paragraph [0093]; storage capacitor Cst) including a first capacitor electrode electrically connected to the gate electrode of the first transistor (FIG. 3; storage capacitor Cst includes an upper [first] electrode that is electrically connected to the gate electrode [region G1] of first transistor T1) and a second capacitor electrode electrically connected to the source electrode of the first transistor (FIG. 3; storage capacitor Cst includes a lower [second] electrode that is electrically connected to the source electrode [region S1] of first transistor T1).
Regarding claim 17, Lee teaches: wherein the connection electrode electrically connects a source electrode of the third transistor with the initialization voltage line (FIGS. 5, 8, 9; paragraphs [0114], [0122]; fourth conductive pattern DP4 [connection electrode] electrically connects initialization voltage wiring VIL to source region [electrode] S3 of third transistor T3 via drain region [electrode] D3).
Regarding claim 20, Lee teaches: further comprising: an auxiliary electrode disposed in the third metal layer, overlapping the initialization voltage line, and electrically connected to the initialization voltage line, wherein the connection electrode and the auxiliary electrode are integral to each other (FIGS. 5. 8, 9; paragraphs [0114]; a left portion of fourth conductive pattern DP4 is interpreted as the “connection electrode” and a right portion of fourth conductive pattern DP4 is interpreted as the “auxiliary electrode).
Claim Rejections - 35 USC § 103
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, as applied to claim 1, as evidenced by Lee 2 et al. (U.S. Pub. 2020/0219450).
Regarding claim 3, Lee fails to explicitly disclose: wherein the initialization voltage line does not receive the high-level voltage or the low-level voltage in a process of aligning the plurality of light-emitting elements.
However, it was well-known and conventional in the art before the effective filing date of Applicant’s claimed invention for an initialization voltage of a display device to be generated separately from high-level and low-level voltages. For evidence please see FIG. 1 and paragraph [0070] of Lee 2.
In light of this well-known and conventional teaching in the art, it would have been obvious for the initialization volage wiring VIL of Lee to only receive an initialization voltage. This modification of Lee, using well-known and conventional teachings as evidenced by Lee 2, requires nothing more than filling in the gaps of Lee as to how differently disclosed voltages are generated. Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of Applicant’s claimed invention to modify the known teachings of Lee using known teachings and known methods to yield predictable results.
Allowable Subject Matter
11. Claims 5 and 18 – 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN A LUBIT whose telephone number is (571)270-3389. The examiner can normally be reached M - F, ~6am - 3pm.
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/RYAN A LUBIT/Primary Examiner, Art Unit 2626
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