Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-8, 10, 11, 14, and 16-18 are rejected under U.S.C. 103 as being unpatentable over Truong et al. (US Pat. 5877636; hereinafter referred to as Truong) in view of Swoboda (US Pat. Pub. 20050218920) in further view of Bryan et al. (US Pat. Pub. 20160308519; hereinafter referred to as Bryan).
As per claims 1 and 10:
Truong teaches a device and a system comprising: a first die comprising a clock signal multiplexer that is configured to provide a test signal as output during a test mode (Truong col. 4-5 lines 67-4, if a test mode is asserted, multiplexer 304 outputs sysclk1 and sysclk2, which are interpreted as test clock signals) and to provide a forwarded clock signal as output during an operational mode (Truong col. 5 lines 5-9, if a test mode is not asserted, multiplexer 304 outputs forwarded clock signals tclk1 and tclk2)
Truong does not explicitly disclose a clock synthesizer. However, Swoboda discloses a clock synthesizer (Swoboda par. 0014, phase locked loop 102 outputs a test clock signal).
Truong and Swoboda are analogous arts because they are in the same field of endeavor of integrated circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Swoboda’s phase locked loop with the device and system of Truong because the claimed invention is merely a combination of known elements, and in the combination each element merely would have performed the same function as it did separately, and one of ordinary skill in the art would have recognized that the results of this combination would have been predictable since it allows for the reduction of timing errors and improving overall system reliability.
Truong and Swoboda do not explicitly disclose a second die that provides the forwarded clock signal to the first die; wherein the first die and the second die are interconnected. However, Bryan discloses a second die that provides the forwarded clock signal to the first die (Bryan par. 0019, clock signal is forwarded from die 1 to die 2); wherein the first die and the second die are interconnected (Bryan par. 0021, the first die and second die are a part of a multi-die package).
Truong, Swoboda, and Bryan are analogous arts because they are in the same field of endeavor of integrated circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Bryan’s forwarded clock signal from a first die to a second die with the device and system of Truong-Swoboda. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it results in a more power-efficient clock distribution (Bryan par. 0006).
As per claims 2 and 14:
Truong, Swoboda, and Bryan further teach the device of claim 1 and the system of claim 10, wherein the clock synthesizer comprises a phase-locked loop (Swoboda par. 0014).
As per claim 3:
Truong, Swoboda, and Bryan further teach the device of claim 1, wherein the test signal and the forwarded clock signal have a same frequency (Swoboda par. 0009, test clock and system clock have the same frequency).
As per claim 4:
Truong, Swoboda, and Bryan further teach the device of claim 1, wherein:
the clock synthesizer (Swoboda par. 0006, PLL 102 is included in integrated circuit 101) and the clock signal multiplexer are elements within a first die (Truong Fig. 3, multiplexer 304 is included in integrated circuit 300); and the forwarded clock signal originates from a second die configured to be stacked with the first die (Bryan par. 0019-0021).
As per claim 5:
Truong, Swoboda, and Bryan further teach the device of claim 4, wherein the output of the clock signal multiplexer provides a clock signal for a plurality of devices on the first die (Truong col. 1 lines 6-11, multiplexing a clock signal for a plurality of circuit elements).
As per claim 6:
Truong, Swoboda, and Bryan further teach the device of claim 5, wherein the output of the clock signal multiplexer is at a base of a clock distribution network of the first die (Bryan par. 0020, clock tree 110).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Bryan’s clock tree with the multiplexer of Truong-Swoboda. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it results in a more power-efficient clock distribution (Bryan par. 0006).
As per claims 7 and 18:
Truong, Swoboda, and Bryan further teach the device of claim 1 and the system of claim 10, further comprising a pad configured to interface with a probe, wherein the pad is operatively connected to the clock synthesizer to provide input to the clock synthesizer (Swoboda par. 0014, reverse termination resistor 17 couples an oscillator unit 11 to PLL 102, wherein the reverse termination resistor 17 acts as a pad).
As per claim 8:
Truong, Swoboda, and Bryan further teach the device of claim 1, wherein the clock synthesizer is configured to receive a clock signal at a first predetermined frequency as input and to produce a clock signal at a second predetermined frequency as output (Swoboda par. 0015, PLL 102 is configured to receive a predetermined input signal frequency and to produce a predetermined output signal frequency).
As per claim 11:
Truong, Swoboda, and Bryan further teach the system of claim 10, wherein the first die further comprises the clock synthesizer (Swoboda par. 0006, PLL 102 is included in integrated circuit 101).
As per claim 16:
Truong, Swoboda, and Bryan further teach the system of claim 10, wherein the output of the clock signal multiplexer provides a clock signal for a plurality of devices on the first die (Truong col. 1 lines 6-11, multiplexing a clock signal for a plurality of circuit elements).
As per claim 17:
Truong, Swoboda, and Bryan further teach the system of claim 10, wherein the output of the clock signal multiplexer is at a base of a clock distribution network of the first die (Bryan par. 0020, clock tree 110).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Bryan’s clock tree with the multiplexer of Truong-Swoboda. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it results in a more power-efficient clock distribution (Bryan par. 0006).
Claims 9 and 12 are rejected under U.S.C. 103 as being unpatentable over Truong-Swoboda-Bryan in further view of Akavaram et al. (US Pat. Pub. 20240202140; hereinafter referred to as Akavaram; filed on 12/14/2022).
As per claim 9:
Truong, Swoboda, and Bryan teach the device of claim 1.
Truong, Swoboda, and Bryan do not explicitly disclose wherein the clock synthesizer is disabled during the operational mode. However, Akavaram discloses wherein the clock synthesizer is disabled during the operational mode (Akavaram par. 0062, disabling PLL circuits).
Truong, Swoboda, Bryan, and Akavaram are analogous arts because they are in the same field of endeavor of integrated circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Akavaram’s disabling PLL circuits with the device of Truong-Swoboda-Bryan. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it results in a reduction of power consumption (Akavaram par. 0062).
As per claim 12:
Truong, Swoboda, and Bryan teach the system of claim 11.
Truong, Swoboda, and Bryan do not explicitly disclose wherein the clock synthesizer is disabled during the operational mode. However, Akavaram discloses wherein the clock synthesizer is disabled during the operational mode (Akavaram par. 0062, disabling PLL circuits).
Truong, Swoboda, Bryan, and Akavaram are analogous arts because they are in the same field of endeavor of integrated circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Akavaram’s disabling PLL circuits with the system of Truong-Swoboda-Bryan. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it results in a reduction of power consumption (Akavaram par. 0062).
Claim 15 is rejected under U.S.C. 103 as being unpatentable over Truong-Swoboda-Bryan in further view of Kim et al. (US Pat. Pub. 20210066145; hereinafter referred to as Kim).
As per claim 15:
Truong, Swoboda, and Bryan teach the system of claim 10.
Truong, Swoboda, and Bryan do not explicitly disclose wherein the first die comprises a memory die. However, Kim discloses wherein the first die comprises a memory die (Kim par. 0006-0007, semiconductor die including nonvolatile memory device).
Truong, Swoboda, Bryan, and Kim are analogous arts because they are in the same field of endeavor of integrated circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Kim’s semiconductor die including nonvolatile memory device with the system of Truong-Swoboda-Bryan. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it allows for memory dies to be tested before coupling (Kim par. 0067).
Claim 19 is rejected under U.S.C. 103 as being unpatentable over Truong-Swoboda in further view of Kim.
As per claim 19:
Truong teaches a method of manufacture comprising: a clock signal multiplexer on the first die is configured to provide a test signal from the clock synthesizer as output during a test mode (Truong col. 4-5 lines 67-4, if a test mode is asserted, multiplexer 304 outputs sysclk1 and sysclk2, which are interpreted as test clock signals) and to provide a forwarded clock signal as output during an operational mode (Truong col. 5 lines 5-9, if a test mode is not asserted, multiplexer 304 outputs forwarded clock signals tclk1 and tclk2)
Truong does not explicitly disclose testing a first die by providing a first clock signal to a clock synthesizer on the first die. However, Swoboda discloses testing a first die by providing a first clock signal to a clock synthesizer on the first die (Swoboda par. 0014, phase locked loop 102 outputs a test clock signal).
Truong and Swoboda are analogous arts because they are in the same field of endeavor of integrated circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Swoboda’s phase locked loop with the device and system of Truong because the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of ordinary skill in the art would have recognized that the results of this combination would have been predictable since it allows for the reduction of timing errors and improving overall system reliability.
Truong and Swoboda do not explicitly disclose coupling the first die to a second die after testing and thereby validating the first die. However, Kim discloses coupling the first die to a second die after testing and thereby validating the first die (Kim par. 0067, after operation S160, couple the first die and the second die. Please note operation S160 is after completing a test operation as stated in Kim par. 0063).
Truong, Swoboda, and Kim are analogous arts because they are in the same field of endeavor of integrated circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Kim’s coupling a first die and a second die after testing with the system of Truong-Swoboda. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it ensures the validation of accurate alignment between the first die and second die (Kim par. 0063).
Allowable Subject Matter
Claims 13 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/JEFFREY ANDREW YANG/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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