Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “THROUGH VIAS FROM STACKED METAL WIRING LAYERS TO IC SUBSTRATE”.
Election/Restrictions
Applicant’s election without traverse of Species I in the reply filed on 4/7/2026 is acknowledged.
Claims 7 and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4/7/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claim(s) 1-2,9-12,16,20 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by US 20100252934 A1 (Law).
Regarding claim 1, Law shows (Fig. 6A-B) a semiconductor chip, comprising:
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a semiconductor substrate (101, para 43);
an integrated circuit layer (102 active device’s circuit layer, para 43) formed on the semiconductor substrate;
a plurality of metal wiring layers (metal layers in 201, para 43) sequentially formed on the semiconductor substrate and the integrated circuit layer;
a first through via structure (303 left, TSV, para 43) bundle (TSVs 601 and ground TSVs 603 for 303, para 44, Fig. 6B) extending in a vertical direction from a first metal wiring layer (lowest wiring layer of 201 closest to leftmost 102) of the plurality of metal wiring layers toward the semiconductor substrate and penetrating through the semiconductor substrate; and
a second through via structure bundle (303 center via bundle, para 44, Fig. 6B as explained before) spaced apart from the first through via structure bundle, extending in the vertical direction from a second metal wiring layer (lowest wiring layer of 201 connected to central 303) of the plurality of metal wiring layers toward the semiconductor substrate, and penetrating through the semiconductor substrate.
Regarding claim 2, Law shows (Fig. 6A-B) wherein a first diameter of each of first through via structures (303 left, TSV, para 43) comprised by the first through via structure bundle (TSVs 601 and ground TSVs 603 for 303, para 44, Fig. 6B) is substantially equal to a second diameter of each of second through via structures comprised by the second through via structure bundle (303 center via bundle, para 44, Fig. 6B as explained before).
Regarding claim 9, Law shows (Fig. 6A-B) wherein a first level of a bottom surface of a lowermost wiring layer (lowest wiring layer in 102 placed on 106) from among the plurality of metal wiring layers is substantially equal to a second level of a top surface of the first through via structure bundle (top surface of 303 left).
Regarding claim 10, Law shows (Fig. 6A-B) further comprising:
an upper pad (613, para 43) electrically connected to an uppermost wiring layer from among the plurality of metal wiring layers, and disposed on the uppermost wiring layer, and a lower pad (401, para 31, RDL line as pad) electrically connected to the first through via structure bundle (303 leftmost as shown in Fig. 6B) and the second through via structure bundle (303 center as shown in Fig. 6B), and disposed on a bottom surface of the semiconductor substrate.
Regarding claim 11, Law shows (Fig. 6A-B) a semiconductor chip, comprising:
a semiconductor substrate (101, para 43) having a first surface (top) and a second surface (bottom) facing each other;
a front end level layer (102 active device’s circuit layer with via through 106, para 43) formed on the first surface of the semiconductor substrate and comprising an integrated circuit layer;
a back end level layer (201 metal layers, para 43) electrically connected to the integrated circuit layer on the front end level layer and comprising a plurality of metal wiring layers;
a first through via structure (303 left, TSV, para 43) bundle (TSVs 601 and ground TSVs 603 for 303, para 44, Fig. 6B) extending in a vertical direction from a first metal wiring layer of the plurality of metal wiring layers toward the semiconductor substrate and
penetrating through the front end level layer, the first surface of the semiconductor substrate, and the second surface of the semiconductor substrate; and
a second through via structure bundle (303 center via bundle, para 44, Fig. 6B as explained before) spaced apart from the first through via structure bundle, extending in the vertical direction from a second metal wiring layer of the plurality of metal wiring layers toward the semiconductor substrate, and
penetrating through at least a part of the back end level layer, the front end level layer, the first surface of the semiconductor substrate, and the second surface of the semiconductor substrate.
Regarding claim 12, Law shows (Fig. 6A-B) wherein a first level of a first top surface of the front end level layer (top of via through 106 connecting 102) is substantially equal to a second level of a second top surface (top surface or leftmost 303) of the first through via structure bundle.
Regarding claim 16, Law shows (Fig. 6A-B) a semiconductor chip, comprising:
a semiconductor substrate (101, para 43);
a front end level layer comprising an integrated circuit layer (102 active device’s circuit layer, para 43) formed on the semiconductor substrate, an interlayer insulation layer (106, para 25) insulating the integrated circuit layer, and a contact plug layer (via contact through 106 connecting 102) electrically connected to the integrated circuit layer within the interlayer insulation layer;
a back end level layer (201, para 43) formed on the front end level layer and comprising a plurality of metal wiring layers sequentially and electrically connected to the contact plug layer, wiring insulation layers insulating between the plurality of metal wiring layers, and a plurality of wiring vias interconnecting the plurality of metal wiring layers within the wiring insulation layers;
a first through via structure (303 left, TSV, para 43) bundle (TSVs 601 and ground TSVs 603 for 303, para 44, Fig. 6B) extending in a vertical direction from a first metal wiring layer of the plurality of metal wiring layers toward the semiconductor substrate and penetrating through the interlayer insulation layer and the semiconductor substrate; and
a second through via structure bundle (303 center via bundle, para 44, Fig. 6B as explained before) spaced apart from the first through via structure bundle, extending in the vertical direction from a second metal wiring layer of the plurality of metal wiring layers toward the semiconductor substrate, and penetrating through the wiring insulation layers, the interlayer insulation layer, and the semiconductor substrate,
wherein the first through via structure bundle is formed in a first keep out zone (106 portion surrounding leftmost 102) located on a first side of the integrated circuit layer, and the second through via structure bundle is formed in a second keep out zone (106 between the right of third 102 and left of fourth 102 from left) located on a second side of the integrated circuit layer.
Regarding claim 20, Law shows (Fig. 6A-B) wherein:
the first keep out zone (106 portion surrounding leftmost 102) and the second keep out zone (106 between the right of third 102 and left of fourth 102 from left) each comprise an insulation material (106), and the first keep out zone and the second keep out zone are spaced apart from each other.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
1. Claim(s) 3, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Law as applied to claim 1.
Regarding claim 3, Law shows (Fig. 6A-B) first through via structures comprises a first via electrode and a first via insulation layer surrounding the first via electrode, each of the second through via structures comprises a second via electrode and a second via insulation layer surrounding the second via electrode.
Law does not specifically show a first thickness of the first via insulation layer is greater than a second thickness of the second via insulation layer.
However, the ordinary artisan would have recognized the thickness of via insulation layer to be a result effective variable affecting the isolation requirement for the signal passing through the via. Thus, it would have been obvious to have first and second via insulation thickness as claimed, since optimum or workable ranges of such variables are discoverable through routine experimentation. See MPEP 2144.05 II.B.
2. Claim(s) 4,5,8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Law as applied to claim 3 or 1 or 11 or 16 above, further in view of US 20220336326 A1 (Ding).
Regarding claim 4, Law shows (Fig. 6A-B) wherein a first length of each of the first through via structures in the vertical direction and a second length of each of the second through via structures in the vertical direction.
Law does not show wherein a first length of each of the first through via structures in the vertical direction is smaller than a second length of each of the second through via structures in the vertical direction.
Ding shows (Fig. 1) wherein a first length of each of the first through via structures (141, para 14) in the vertical direction is smaller than a second length of each of the second through via structures (142, para 14) in the vertical direction.
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Ding, with unequal vias, to the invention of Law.
The motivation to do so is that the combination produces the predictable result of having through-vias from different levels of wiring layers (WL1, WL4).
Regarding claim 5, Law as previously modified with Ding shows the first through via structure bundle (Law first through via modified with Ding, 141, para 48, Ding) comprises a signal transfer via structure, and the second through via structure bundle (Law 303 center via bundle, para 44, Fig. 6B as explained before, where 601 is power via) comprises a power transmission via structure.
Regarding claim 8, Law as previously modified with Ding shows wherein:
the first through via structure bundle (151, Ding) and the second through via structure bundle are each surrounded by an insulation material (152, Ding).
Regarding claim 13, Law as previously modified with Ding shows a first diameter of each of first through via structures comprised by the first through via structure bundle is substantially equal to a second diameter of each of second through via structures comprised by the second through via structure bundle (Law), each of the first through via structures comprises a first via electrode (Ding) and a first via insulation layer surrounding the first via electrode and having a first thickness and each of the second through via structures comprises a second via electrode and a second via insulation layer surrounding the second via electrode and having a second thickness (Ding).
Law in combination with Ding does not show second thickness that is thinner than the first thickness.
However, the ordinary artisan would have recognized the thickness of via insulation layer to be a result effective variable affecting the isolation requirement for the signal passing through the via. Thus, it would have been obvious to have first and second via insulation thickness as claimed, since optimum or workable ranges of such variables are discoverable through routine experimentation. See MPEP 2144.05 II.B.
Regarding claim 17, the prior art/s as noted in the above rejection of claim 13, discloses the entire claimed invention.
Allowable Subject Matter
Claims 6,14-15,18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 6, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “the signal transfer via structure is disposed at a center of the first through via structure bundle, the first through via structure bundle comprises a plurality of ground via structures disposed around the signal transfer via structure, and the second through via structure bundle comprises a plurality of power transmission via structures”.
Regarding claim 14 or claim 18, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “the first through via structure bundle comprises a signal transfer via structure disposed at a center of the first through via structure bundle and a plurality of ground via structures disposed around the signal transfer via structure, and
the second through via structure bundle comprises a plurality of power transmission via structures”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WASIUL HAIDER whose telephone number is (571)272-1554. The examiner can normally be reached M-F 9 a.m. - 6 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WASIUL HAIDER/Primary Examiner, Art Unit 2812
Prosecution Insights