Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/15/2023 are being considered by the examiner.
Claim Objections
Claim 15 is objected to because of the following informality:
In line 2, "comprise" should read "and". Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-11, and 15-20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Oh et al. (US 2022/0384311 A1).
Regarding claim 1, Oh et al. teaches a semiconductor structure (FIG. 30), comprising:
a first semiconductor fin ([0148]), first fin type pattern 112 of F1) disposed on a first source/drain region ([0157], first source/drain region 160) of a first nanosheet transistor device (first electronic element TR1);
a second semiconductor fin ([0148], second fin type pattern 212 of F2) disposed on a second source/drain region ([0157], second source/drain region 260) of a second nanosheet transistor device (second electronic element TR2);
a first dielectric etch stop layer ([0046], first gate dielectric film 120) disposed on the first semiconductor fin; and
a second dielectric etch stop layer ([0046], second gate dielectric film 220) disposed on the second semiconductor fin;
wherein the first semiconductor fin and the second semiconductor fin are of a uniform height (FIG. 16 and [0148]: first and second active patterns F1, F2 including first and second fin type patterns 112, 212 in regions I and II, in Z1 and Z2 direction).
Regarding claim 2, Oh et al. teaches the semiconductor structure according to claim 1, wherein the first semiconductor fin ([0148]), first fin type pattern 112) and the first dielectric etch stop layer ([0046], gate dielectric film 120) have a same width (FIG. 17, first region I: 112 and 120 in X1 direction, extending along upper side of field insulating film 105 in [0046]), and the second semiconductor fin ([0148]), second fin type pattern 212), and the second semiconductor fin ([0148]), second fin type pattern 212) and the second dielectric etch stop layer ([0046], gate dielectric film 220) have a same width (FIG. 17, second region II: 212 and 220 in X2 direction, extending along upper side of field insulating film 105 in [0046]).
Regarding claim 3, Oh et al. teaches the semiconductor structure according to claim 1, wherein the first dielectric etch stop layer ([0046], gate dielectric film 120) and the second dielectric etch stop layer ([0046], gate dielectric film 220) each comprises a buried oxide layer ([0047], comprised of silicon nitride and interposed ([0046]) between active patterns F1,F2 and gate electrodes 130, 230, wherein gate electrodes 130, 230 comprise silicon ([0044]) and active patterns F1,F2 on substrate 100 comprises SOI ([0028])).
Regarding claim 4, Oh et al. teaches the semiconductor structure according to claim 1, wherein the first dielectric etch stop layer ([0046], gate dielectric film 120) and the second dielectric etch stop layer [0046], gate dielectric film 220) each comprises an epitaxial oxide layer ([0054], epitaxial layers formed on both first and second active patterns F1 and F2).
Regarding claim 5, Oh et al. teaches the semiconductor structure according to claim 1, wherein the first semiconductor fin (first fin type pattern 112) and the second semiconductor fin (second fin type pattern 212) comprise a first backside silicon fin ([0031], substrate 100 on which 112 is on, includes a backside opposite to the frontside) and a second backside silicon fin ([0031], substrate 100 on which 212 is on, includes a backside opposite to the frontside).
Regarding claim 6, Oh et al. teaches the semiconductor structure according to claim 1, further comprising:
a middle-of-the-line contact ([0094] and FIG. 15, backside wiring patterns BM1) disposed on a given one of the first source/drain region ([0157], first source/drain region 160) and the second source/drain region ([0157], second source/drain region 260); and
a metal via ([0111] and FIG. 15, through conductive film 292) connecting a backside power rail ([0085] and FIG. 15, fourth power wiring PW22) to the middle-of-the-line contact.
Regarding claim 7, Oh et al. teaches the semiconductor structure according to claim 6, further comprising a backside power delivery network ([0108], power delivery network (PDN), backside of substrate 100) disposed over the backside power rail ([0085] and FIG. 15, fourth power wiring PW22).
Regarding claim 8, Oh et al. teaches a semiconductor structure (FIG. 30), comprising:
a first silicon fin ([0148]), first fin type pattern 112 of F1) disposed on a first source/drain region ([0157], first source/drain region 160) of a first nanosheet transistor device (first electronic element TR1);
a second silicon fin ([0148], second fin type pattern 212 of F2) disposed on a second source/drain region ([0157], second source/drain region 260) of a second nanosheet transistor device (second electronic element TR2);
a first dielectric etch stop layer ([0046], first gate dielectric film 120) disposed on the first silicon fin; and
a second dielectric etch stop layer ([0046], second gate dielectric film 220) disposed on the second silicon fin;
wherein the first silicon fin and the second silicon fin are disposed between adjacent shallow trench isolation regions ([0038] and FIG. 4, field insulating film 105 of first and second element separation trenches 100t1 and 100t2); and
wherein the first silicon fin and the second silicon fin are of a uniform height (FIG. 16 and [0148]: first and second active patterns F1, F2 including first and second fin type patterns 112, 212 in regions I and II, in Z1 and Z2 direction).
Regarding claim 9, Oh et al. teaches the semiconductor structure according to claim 8, wherein the first dielectric etch stop layer (first gate dielectric films 120) is a first lattice matched etch stop layer ([0049], includes silicon oxide) and the second dielectric etch stop layer (second gate dielectric films 220) is a second lattice matched etch stop layer ([0049], includes hafnium oxide).
Regarding claim 10, Oh et al. teaches the semiconductor structure according to claim 9, wherein the first silicon fin (first fin type pattern 112 of F1) and the second silicon fin (second fin type pattern 212 of F2) are each epitaxially grown ([0054], epitaxial layer formed on the first, second active patterns F1, F2 in first, second source/drain regions 160, 260) on the first lattice matched etch stop layer ([0049], first gate dielectric film 120 including silicon oxide) and the second lattice matched etch stop layer ([0049], second gate dielectric film 220 including hafnium oxide).
Regarding claim 11, Oh et al. teaches the semiconductor structure according to claim 9, wherein the first lattice matched etch stop layer ([0049], first gate dielectric film 120 including silicon oxide) comprises a first epitaxial oxide layer ([0059], includes ferroelectric material film including hafnium oxide ([0062])) and the second lattice matched etch stop layer ([0049], second gate dielectric film 220 including hafnium oxide) comprises a second epitaxial oxide layer ([0059], includes paraelectric material film including hafnium oxide ([0067])).
Regarding claim 15, Oh et al. teaches the semiconductor structure according to claim 8, wherein the first silicon fin ([0148]), first fin type pattern 112 of F1) and the second silicon fin ([0148], second fin type pattern 212 of F2) are a first backside silicon fin ([0031], substrate 100 on which 112 is on, includes a backside opposite to the frontside) and a second backside silicon fin ([0031], substrate 100 on which 212 is on, includes a backside opposite to the frontside).
Regarding claim 16, Oh et al. teaches the semiconductor structure according to claim 8, further comprising:
a middle-of-the-line contact ([0094] and FIG. 15, backside wiring patterns BM1) disposed on a given one of the first source/drain region ([0157], first source/drain region 160) and the second source/drain region ([0157], second source/drain region 260); and
a metal via ([0111] and FIG. 15, through conductive film 292) connecting a backside power rail ([0085] and FIG. 15, fourth power wiring PW22) to the middle-of-the-line contact.
Regarding claim 17, Oh et al. teaches the semiconductor structure according to claim 16, further comprising a backside power delivery network ([0108], power delivery network (PDN), backside of substrate 100) disposed over the backside power rail ([0085] and FIG. 15, fourth power wiring PW22).
Regarding claim 18, Oh et al. teaches an integrated circuit ([0026], made by integrating various semiconductor devices, such as CMOS imaging sensor, onto it), comprising:
one or more semiconductor structures (FIG. 4), wherein at least one of the one or more semiconductor structures comprises:
a first semiconductor fin ([0148]), first fin type pattern 112 of F1) disposed on a first source/drain region ([0157], first source/drain region 160) of a first nanosheet transistor device (first electronic element TR1);
a second semiconductor fin ([0148], second fin type pattern 212 of F2) disposed on a second source/drain region ([0157], second source/drain region 260) of a second nanosheet transistor device (second electronic element TR2);
a first dielectric etch stop layer ([0046], first gate dielectric film 120) disposed on the first semiconductor fin; and
a second dielectric etch stop layer ([0046], second gate dielectric film 220) disposed on the second semiconductor fin;
wherein the first semiconductor fin and the second semiconductor fin are of a uniform height (FIG. 16 and [0148]: first and second active patterns F1, F2 including first and second fin type patterns 112, 212 in regions I and II, in Z1 and Z2 direction).
Regarding claim 19, Oh et al. teaches the integrated circuit according to claim 18, further comprising:
a middle-of-the-line contact ([0094] and FIG. 15, backside wiring patterns BM1) disposed on a given one of the first source/drain region ([0157], first source/drain region 160) and the second source/drain region ([0157], second source/drain region 260); and
a metal via ([0111] and FIG. 15, through conductive film 292) connecting a backside power rail ([0085] and FIG. 15, fourth power wiring PW22) to the middle-of-the-line contact.
Regarding claim 20, Oh et al. teaches the integrated circuit according to claim 19, further comprising: a backside power delivery network ([0108], power delivery network (PDN), backside of substrate 100) disposed over the backside power rail ([0085] and FIG. 15, fourth power wiring PW22).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2022/0384311 A1) in view of Reznicek et al. (US 2021/0175285 A1).
Regarding claim 12, Oh et al. teaches the semiconductor structure according to claim 11, wherein the first epitaxial oxide layer ([0059], includes ferroelectric material film including hafnium oxide ([0062]))
and the second epitaxial oxide layer ([0059], includes paraelectric material film including hafnium oxide ([0067])) each comprises a layer of a mixed rare earth oxide ([0062], ferroelectric material film including hafnium oxide, doped with lanthanum (La) and yttrium (Y), ([0063])), the mixed rare earth oxide being lattice-matched ([0062], doped with lanthanum (La) and yttrium (Y)) to the first silicon fin ([0148]), first fin type pattern 112 of F1) and the second silicon fin ([0148], second fin type pattern 212 of F2).
Oh et al. fails to explicitly teach the mixed rare earth oxide being single crystal.
However, Reznicek et al. teaches the mixed rare earth oxide ([0042], epitaxial oxide layer 112 comprises (La.sub.xY.sub.1−x).sub.2O.sub.3) being single crystal ([0041], single crystalline structure).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the mixed rare earth oxide taught in Oh et al. to have been grown as a single crystal, as taught in Reznicek et al. Epitaxial growth of single crystal (as compared to a polycrystalline structure) allows precise lattice matching and uniformity in composition and thickness, and the resulting homogenous conductivity enables high carrier mobility and thus efficient routing of signals connecting the IC elements on the substrate. The uniform thickness of the epitaxial oxide layer further allows for a smaller silicon fin height and thus a shorter metal via, resulting in an improved aspect ratio—a solution that Reznicek et al. also similarly teaches (saving space) for their recited invention.
Regarding claim 13, Oh et al. in view of Reznicek et al. teaches the semiconductor structure according to claim 12. Reznicek et al. teaches wherein the mixed rare earth oxide ([0042], epitaxial oxide layer 112 comprises (La.sub.xY.sub.1−x).sub.2O.sub.3) comprises a compound having a chemical formula (AxB1-x)2O3, wherein A represents a first rare earth element (La or lanthanum) and B represents a second rare earth element (Y or yttrium).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the first and second epitaxial oxide layers comprising hafnium oxide doped with La and Y, as taught in Oh et al., to instead comprise Lanthanum Yttrium oxide, as taught in Reznicek et al. Lanthanum Yttrium oxide has intrinsic lattice stability as Lanthanum oxide has a high dielectric constant k, which enables strong capacitance in thin layers. The high-k dielectric also heightens compatibility with CMOS manufacture, a goal recited in both Oh et al. and Reznicek et al. for their respective semiconductor structures. The uniform and well-defined lattice structure of Lanthanum Yttrium oxide, to further clarify from above, enables etch stop uniformity and provides a simpler, single-step deposition process of manufacture. The stability of Lanthanum Yttrium oxide at higher processing temperatures (thermal stability) further provides protection against crystalline silicon from diffusing into the silicon substrate.
Regarding claim 14, Oh et al. in view of Reznicek et al. teaches the semiconductor structure according to claim 12. Reznicek et al. teaches wherein he mixed rare earth oxide ([0042], epitaxial oxide layer 112) comprises (LaxY1−x)2O3 ([0042], La.sub.xY.sub.1−x).sub.2O.sub.3) and x is 0.33 ([0042], wherein x is 0.33).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the first and second epitaxial oxide layers comprising hafnium oxide doped with La and Y, as taught in Oh et al., to instead comprise Lanthanum Yttrium oxide (LaxY1−x)2O3 ) wherein x=0.33, as taught in Reznicek et al. The La to Y ratio at x=0.33 (for example, La: 33% and Y: 67%) provides maximal mismatch to induce lattice strain and disorder (for properties like thermal expansion and ionic conductivity in high-k dielectrics) without exceeding solubility limit and thus potential phase separation. Structural homogeneity is thereby enhanced and ensures evenly distributed mistfit strain, which reduces likelihood of cracks, and thus enhances lattice matching of the epitaxial oxide layer to the silicon substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEANNE M KIM whose telephone number is (571)272-8768. The examiner can normally be reached Monday-Thursday 8:00-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JEANNE MYON KIM/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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