DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
2. Applicant's election with traverse of Species I in the reply filed on May 19, 2026 is acknowledged. The traversal is on the grounds that the pending claims were improperly divided into the two mutually exclusive species (specifically. The examiner acknowledges that claims have been improperly mapped, will regroup claims 2 and 11 to be in Species II, and examine pending claims 1, 3-10, and 12-17 as generic claims. Therefore, as Species I was elected, claims 1, 3-10, and 12-17 will be examined.
Additionally, examiner acknowledges that there are no process or method claims pending, and withdraws the product/process restriction.
The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on December 15, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner except as otherwise indicated.
Claim Rejections - 35 USC § 102
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1, 3-10, and 11-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al (US 2024/0274676, hereafter Lee).
Regarding claim 1, Lee discloses a semiconductor device (Fig. 24A 10’), comprising:
an active part (NC+G1) that includes a semiconductor channel (Fig. 24B NC) and a gate structure (Fig. 24B G1);
a frontside part (136+V0+M1) that includes a frontside electrical contact (Fig. 24B V0) to the active part (NC+G1);
a backside part (106+BC+BM) that includes a backside electrical contact (Fig. 24B BC) to the active part (NC+G1);
and a lower gate cap (Fig. 24E 103) including a first region that is in contact (Fig. 24E) with a shallow trench isolation (STI) structure (Fig. 24E 106) of the backside part (BC+BM) and a second region (Fig. 24B) that is in contact (Fig. 24B) with a surface of the backside electrical contact (BC),
wherein the lower gate cap (103) electrically insulates ([0059]) the gate structure (G1) from the backside electrical contact (BC).
Although Lee does not explicitly disclose the lower gate cap electrically insulating the gate structure from the backside electrical contact, Lee discloses that the lower gate cap is formed from a silicon oxide ([0051]), which is known in the art to be an electrical insulator.
Regarding claim 3, Lee discloses the semiconductor device of claim 1, wherein the lower gate cap (103) includes a dielectric material ([0051]) that is distinct from a dielectric material ([0053]) of the STI structure (106).
Regarding claim 5, Lee discloses the semiconductor device of claim 1, further comprising a dielectric backside remnant (Fig. 22B 106 after etch; [0136]) between the backside electrical contact (BC) and the semiconductor channel (NC).
Regarding claim 6, Lee discloses the semiconductor device of claim 5, further comprising a dielectric isolation layer (Fig. 22B 111) between the dielectric backside remnant (106 after etch) and the semiconductor channel (NC).
Regarding claim 7, Lee discloses the semiconductor device of claim 6, wherein the dielectric backside remnant (106 after etch) is silicon dioxide ([0133]) and the dielectric isolation layer (111) is silicon nitride ([0071]).
Regarding claim 8, Lee discloses the semiconductor device of claim 1, wherein the frontside part further includes frontside back-end-of-line (BEOL) layers (Fig. 24B M1) and the backside part further includes backside BEOL layers (Fig. 24B BM).
Regarding claim 9, Lee discloses the semiconductor device of claim 1, wherein the semiconductor channel (NC) includes a plurality of vertically aligned silicon nanosheets (Fig. 24B NC; [0033]).
Regarding claim 10, Lee discloses a semiconductor device (Fig. 24A 10’), comprising:
an active part (NC+G1/2+SD1/SD2) that includes a semiconductor channel (Fig. 24B NC), a gate structure (Fig. 24B G1), and source/drain regions (Fig. 24B SD1/SD2) in contact with the semiconductor channel (NC);
a frontside part (136+V0+M1) that includes a frontside electrical contact (Fig. 24B V0) to the active part (NC+G1/2+SD1/SD2);
a backside part (106+BC+BM) that includes a backside electrical contact (Fig. 24B BC) to one of the source/drain regions (Fig. 24B SD2) in the active part (NC+G1/2+SD1/SD2) and a shallow trench isolation (STI) structure (Fig. 24E 106) formed from a first dielectric material ([0053]);
and a lower gate cap (Fig. 24B 103) formed from a second dielectric material ([0051]) distinct from the first dielectric material ([0053]), the lower gate cap (103) including a first region that is in contact (Fig. 24E) with the STI structure (106) of the backside part (106+BC+BM) and a second region that is in contact (Fig. 24B) with a surface of the backside electrical contact (BC),
wherein the lower gate cap (103) electrically insulates ([0059]) the gate structure (G1) from the backside electrical contact (BC).
Although Lee does not explicitly disclose the lower gate cap electrically insulating the gate structure from the backside electrical contact, Lee discloses that the lower gate cap is formed from a silicon oxide ([0051]), which is known in the art to be an electrical insulator.
Regarding claim 13, Lee discloses the semiconductor device of claim 10, further comprising a dielectric backside remnant (Fig. 22B 106 after etch; [0136]) between the backside electrical contact (BC) and the semiconductor channel (NC).
Regarding claim 14, Lee discloses the semiconductor device of claim 13, further comprising a dielectric isolation layer (Fig. 22B 111) between the dielectric backside remnant (106 after etch) and the semiconductor channel (NC).
Regarding claim 15, Lee discloses the semiconductor device of claim 14, wherein the dielectric backside remnant (106 after etch) is silicon dioxide ([0133]) and the dielectric isolation layer (111) is silicon nitride ([0071]).
Regarding claim 16, Lee discloses the semiconductor device of claim 10, wherein the frontside part further includes frontside back-end-of-line (BEOL) layers (Fig. 24B M1) and the backside part further includes backside BEOL layers (Fig. 24B BM).
Regarding claim 17, Lee discloses the semiconductor device of claim 10, wherein the semiconductor channel (NC) includes a plurality of vertically aligned silicon nanosheets (Fig. 24B NC; [0033]).
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 4 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Huang et al (US 2021/0202385 A1, hereafter Huang).
Regarding claim 4, Lee discloses the semiconductor device of claim 3, wherein the dielectric material ([0051]) of the lower gate cap (103) is formed from a dielectric material ([0051]).
Lee does not disclose a dielectric material selected from the group consisting of SiC and SiOC.
Huang discloses a lower gate cap (Fig. 19 122) formed from a dielectric material selected from the group consisting of SiOC ([0017]). Huang is analogous to Lee in the art of FinFETs.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace the material of the lower gate cap of Lee with the material of Huang to provide better thermal insulation while maintain similar electrical insulative properties.
Regarding claim 12, Lee discloses the semiconductor device of claim 10, wherein the dielectric material ([0051]) of the lower gate cap (103) is formed from a dielectric material ([0051]).
Lee does not disclose a dielectric material selected from the group consisting of SiC and SiOC.
Huang discloses a lower gate cap (Fig. 19 122) formed from a dielectric material selected from the group consisting of SiOC ([0017]). Huang is analogous to Lee in the art of FinFETs.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to replace the material of the lower gate cap of Lee with the material of Huang to provide better thermal insulation while maintain similar electrical insulative properties.
Conclusion
8. The following art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Lee et al (US 2024/0203882 A1) discloses a gate-all-around (GAA) FinFET with backside and frontside contacts
Hsu et al (US 2021/0359091 A1) discloses a GAA FinFET with STI regions and backside and frontside contacts.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL B SUN whose telephone number is (571)699-0231. The examiner can normally be reached Mon-Fri 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL B SUN/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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