Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested:
“A Driving Circuit in Non-Active Area for Driving Display Panel”
Claim Objections
Claim 8 is objected to because of the following informalities: the “a third ling” in line 9 should be “a third lingk”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 5-6 are rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by Kim (US 20200411630).
Regarding claim 1. Fig 1 (plan view of display), Fig 2 (perspective view of display Fig 1), Fig 3 (a portion view of Fig 1/Fig 2) and Fig 14 (a portion view of Fig 1/Fig 2) of Kim disclose A display device 10 (Fig 1/Fig 2) comprising:
a substrate 100 (Fig 2, [0055]: also 110) including an active area (Fig 1: DA) and a non-active area (Fig 1: outer area of DA including SA and BA) which surrounds the active area (Fig 1);
a plurality of circuit films 300 ([0053]: flexible printed circuit board) positioned at a first side (the side along D1) of the substrate (Fig 2) and positioned in the non-active area, the plurality of circuit films spaced apart from one another (Fig 1); and
a first link portion (Fig 1: the first ‘FL’ portion from very left) connected to a connection wiring ([0053]: “transfer a data signal to the transfer wiring of the display panel”) of the plurality of circuit films positioned in the non-active area (Fig 1),
wherein the first link portion comprises:
a first metal layer (SC1a) disposed on the substrate (Fig 14, [0088]: SC1a on upper side of 110);
a buffer layer 152 covering an upper surface of the substrate and the first metal layer (Fig 14);
a gate insulating film 142 ([0061]/[0089]: the second insulation layer 140 is the same as 140 which is gate insulation film in display ‘DA’ region shown Fig 3) disposed on the buffer layer (Fig 14: 142 is on bottom surface side of 152);
a first signal wiring (SC2a) disposed on the gate insulating film (Fig 14);
a planarization layer 162 covering an upper surface of the buffer layer and the first signal wiring (Fig 14); and
a first link wiring (SC3a) disposed on the planarization layer (Fig 14),
wherein the first link wiring and the first signal wiring are electrically connected through contact holes (Fig 14: the holes where the two of SC3b are located and thus they are electrically connected via SC3b) and the first signal wiring and the first metal layer are electrically connected through the contact holes (Fig 14: the holes where the two of SC2b are located and thus they are electrically conned via SC2b).
Regarding claim 5. Kim discloses The display device of claim 1, wherein the first signal wiring is a driving voltage wiring ([0046]: ‘FL transferring a data signal to the data line DL” which means FL in a display panel that transfers a data signal to a data line (DL) effectively delivers a driving voltage to the pixel element).
Regarding claim 6. Kim discloses The display device of claim 1, further comprising:
a first bar 400 parallel to the first side (Fig 2), and disposed in the non-active area (Fig 2); and
a second link portion (Fig 1: the second ‘FL’ portion from very left) connected to the first bar (Fig 1/Fig 2),
wherein the second link portion comprises:
a second metal layer (SC1a) disposed on the substrate (Fig 14, [0088]: SC1a on upper side of 110), wherein the buffer layer 152 covers the upper surface of the substrate and the second metal layer (Fig 14); and the gate insulating film 142 disposed on the buffer layer (Fig 14: 142 is on bottom surface side of 152);
a second signal wiring (SC2a) disposed on the gate insulating film (Fig 14),
wherein the planarization layer 162 covers the upper surface of the buffer layer and the second signal wiring (Fig 14); and
a second link wiring (SC3a) disposed on the planarization layer (Fig 14),
wherein the second link wiring and the second signal wiring are electrically connected through contact holes (Fig 14: the holes where the two of SC3b are located and thus they are electrically connected via SC3b) and the second signal wiring and the second metal layer are electrically connected through the contact holes (Fig 14: the holes where the two of SC2b are located and thus they are electrically conned via SC2b).
Allowable Subject Matter
Claims 2-4 and 7-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “a transparent conductive oxide layer and an auxiliary metal layer which is disposed on the transparent conductive oxide layer, and the first link portion further comprises a low-temperature passivation layer covering an upper surface of the planarization layer and the first link wiring”.
Regarding claim 7. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “a transparent conductive oxide layer and an auxiliary metal layer which is disposed on the transparent conductive oxide layer, and the second link portion further comprises a low-temperature passivation layer covering an upper surface of the planarization layer and the second link wiring”.
Regarding claim 8. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “an electrode pattern positioned between first link portions of first signal wirings; and a third link portion connected to the electrode pattern, the third link portion comprises: a third metal layer disposed on the substrate, the buffer layer disposed on the third metal layer, and the gate insulating film is disposed on the buffer layer; a third signal wiring disposed on the gate insulating film, the planarization layer disposed on the third signal wiring; and a third ling wiring disposed on the planarization layer, the third link wiring and the third signal wiring and the third signal wiring and the third metal layer are electrically connected through contact holes, respectively”.
Regarding claim 12. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “a fourth link portion connected to the light emitting element, the fourth link portion comprises: a fourth metal layer disposed on the substrate, wherein the buffer layer is disposed on the fourth metal layer, and the gate insulating film is disposed on the buffer layer; a fourth signal wiring disposed on the gate insulating film, wherein the planarization layer is disposed on the fourth signal wiring; and a fourth link wiring disposed on the planarization layer, the fourth link wiring and the fourth signal wiring are electrically connected through contact holes and the fourth signal wiring and the fourth metal layer are electrically connected through the contact holes”.
Regarding claim 15. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “a clock wiring unit disposed in the non-active area, and including a clock wiring; and a fifth link portion connected to the clock wiring, the fifth link portion comprises: a fifth metal layer disposed on the substrate, wherein the buffer layer is disposed on the fifth metal layer, and the gate insulating film is disposed on the buffer layer; a fifth signal wiring disposed on the gate insulating film, wherein the planarization layer is disposed on the fifth signal wiring; and a fifth link wiring disposed on the planarization layer, the fifth link wiring and the fifth signal wiring are electrically connected through contact holes and the fifth signal wiring and the fifth metal layer are electrically connected through the contact holes”.
Regarding claim 17. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “a gate driving circuit unit disposed in the non-active area, and including a thin film transistor; and a gate power wiring connected to the thin film transistor disposed on the substrate, the planarization layer is disposed on the thin film transistor, the gate power wiring is disposed on the planarization layer, and the gate power wiring and a source electrode or a drain electrode of the thin film transistor are electrically connected”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812