Prosecution Insights
Last updated: May 29, 2026
Application No. 18/541,571

Engineered Interconnect Structures for Enhanced Bonding Strength

Non-Final OA §102§103
Filed
Dec 15, 2023
Examiner
ALAM, MOHAMMED R
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Wolfspeed, Inc.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
501 granted / 562 resolved
+21.1% vs TC avg
Moderate +6% lift
Without
With
+6.2%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
15 currently pending
Career history
580
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
75.4%
+35.4% vs TC avg
§102
10.6%
-29.4% vs TC avg
§112
6.8%
-33.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 562 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claim 1, 3, 24, 31, 33, and 54 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Heng (US patent 9,679,832 B1), hereinafter referred to as Heng832. Regarding claim 1, Heng832 teaches a power semiconductor device package (fig. 1a-1b and related text), comprising: one or more semiconductor die (12a/12b/12c, lines 36-58 of col. 2); a submount (14a/14b/14c, lines 36-58 of col. 2), wherein the one or more semiconductor die are on the submount (fig. 1a-1b); and at least one interconnect structure (16/20, lines 60-67 of col. 2 and lines 1-30 of col. 3), the at least one interconnect structure comprising at least one texturized surface (lines 1-30 of col. 3, fig. 1b). Regarding claim 3, Heng832 teaches wherein the interconnect structure is a wire bond structure (fig. 1b)., a ribbon attach structure, or a clip attach structure (fig. 1b). Regarding claim 24, Heng832 discloses wherein the at least one texturized surface comprises a localized area of a surface of the interconnect structure (fig. 1b). Regarding claim 31, Heng832 discloses wherein the power semiconductor device package is a power module or a discrete semiconductor package (lines 46-58 of col. 2, fig. 1a). Regarding claim 33, Heng832 discloses method (a method of making a device of fig. 1a-1b), comprising: providing an interconnect structure (16/20, lines 60-67 of col. 2 and lines 1-30 of col. 3) for a power semiconductor device package (lines 36-58 of col. 2, fig. 1a); and processing at least one surface of the interconnect structure using a texturizing process to provide at least one texturized surface on the interconnect structure (lines 1-30 of col. 3, fig. 1b). Regarding claim 54, Heng832 discloses an interconnect structure (16/20, lines 60-67 of col. 2 and lines 1-30 of col. 3, fig. 1a-1b) for a power semiconductor device package (lines 36-58 of col. 2, fig. 1a), comprising: a conductive structure (16, lines 60-67 of col. 2 and lines 1-30 of col. 3, fig. 1a-1b); and at least one texturized surface on the conductive structure (lines 1-30 of col. 3, fig. 1b). Claim 1 and 25-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hashizume (US publication 2019/0311974 A1), hereinafter referred to as Hashizume. Regarding claim 1, Hashizume teaches a power semiconductor device package (fig. 7-8 and related text), comprising: one or more semiconductor die (CHIP, [0040], fig. 7); a submount (a portion of TAB where CHIP is mounted), wherein the one or more semiconductor die are on the submount (fig. 7); and at least one interconnect structure (TAB/LD/W, [0038]), the at least one interconnect structure comprising at least one texturized surface (fig. 7). Regarding claim 25, Hashizume discloses wherein the interconnect structure comprises a plurality of texturized surfaces (fig. 7). Regarding claim 26, Hashizume discloses wherein the submount is a lead frame, wherein the lead frame comprises a texturized surface (fig. 7-8). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Heng832, as applied to claim 1 above, and further in view of Lee et al. (US publication 2024/0258210 A1), hereinafter referred to as Lee210. Regarding claim 4, Heng832 discloses all the limitations of claim 1 as discussed above on which this claim depends. Heng832 does not explicitly teach wherein the interconnect structure has an annular cross-section, wherein the at least one texturized surface comprises at least a portion of a surface about the annular cross-section. Lee210 teaches wherein the interconnect structure has an annular cross-section (round shape 1 or 2 as shown in fig. 5 will have an annular cross-section), wherein the at least one texturized surface comprises at least a portion of a surface about the annular cross-section (fig. 3d-3e). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Heng832 with that of Lee210 so that wherein the interconnect structure has an annular cross-section, wherein the at least one texturized surface comprises at least a portion of a surface about the annular cross-section to restrict flow of die attach adhesive and/or resin bleed from the die attach adhesive ([0010]). Regarding claim 5, Heng832 discloses all the limitations of claim 1 as discussed above on which this claim depends. Heng832 does not explicitly teach wherein the interconnect structure has a polygonal cross-section, wherein the at least one texturized surface comprises at least one polygonal surface about the polygonal cross-section. Lee210 teaches wherein the interconnect structure has a polygonal cross-section (fig. 5), wherein the at least one texturized surface comprises at least one polygonal surface about the polygonal cross-section (fig. 3d-3e). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Heng832 with that of Lee210 so that wherein the interconnect structure has a polygonal cross-section, wherein the at least one texturized surface comprises at least one polygonal surface about the polygonal cross-section to restrict flow of die attach adhesive and/or resin bleed from the die attach adhesive ([0010]). Claim 2, 4-7, 9-11, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Hashizume, as applied to claim 1 above, and further in view of Lee et al. (US publication 2024/0258210 A1), hereinafter referred to as Lee210. Regarding claim 2, Hashizume discloses all the limitations of claim 1 as discussed above on which this claim depends. Hashizume does not explicitly teach wherein the at least one texturized surface has a surface roughness Ra in a range of about 5 microns to about 100 microns. Lee210 teaches wherein the at least one texturized surface has a surface roughness Ra in a range of about 5 microns to about 100 microns ([0042]). Furthermore, it is obvious to one of ordinary skill in the art to determine the workable or optimal range such as a surface roughness through routine experimentation and optimization to obtain optimal or desired performance. Since Applicant has not shown that these ranges are novel and that they would not have been found through routine experimentation, it would have been obvious to one having ordinary skill in the art to optimize these ranges in order to meet customer requirements and to obtain optimal or desired performance, and it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Hashizume with that of Lee210 so that wherein the at least one texturized surface has a surface roughness Ra in a range of about 5 microns to about 100 microns to restrict flow of die attach adhesive and/or resin bleed from the die attach adhesive ([0010]). Regarding claim 4, Hashizume discloses all the limitations of claim 1 as discussed above on which this claim depends. Hashizume does not explicitly teach wherein the interconnect structure has an annular cross-section, wherein the at least one texturized surface comprises at least a portion of a surface about the annular cross-section. Lee210 teaches wherein the interconnect structure has an annular cross-section (round shape 1 or 2 as shown in fig. 5 will have an annular cross-section), wherein the at least one texturized surface comprises at least a portion of a surface about the annular cross-section (fig. 3d-3e). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Hashizume with that of Lee210 so that wherein the interconnect structure has an annular cross-section, wherein the at least one texturized surface comprises at least a portion of a surface about the annular cross-section to restrict flow of die attach adhesive and/or resin bleed from the die attach adhesive ([0010]). Regarding claim 5, Hashizume discloses all the limitations of claim 1 as discussed above on which this claim depends. Hashizume does not explicitly teach wherein the interconnect structure has a polygonal cross-section, wherein the at least one texturized surface comprises at least one polygonal surface about the polygonal cross-section. Lee210 teaches wherein the interconnect structure has a polygonal cross-section (fig. 5), wherein the at least one texturized surface comprises at least one polygonal surface about the polygonal cross-section (fig. 3d-3e). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Hashizume with that of Lee210 so that wherein the interconnect structure has a polygonal cross-section, wherein the at least one texturized surface comprises at least one polygonal surface about the polygonal cross-section to restrict flow of die attach adhesive and/or resin bleed from the die attach adhesive ([0010]). Regarding claim 6, Hashizume discloses all the limitations of claim 1 as discussed above on which this claim depends. Hashizume does not explicitly teach wherein the at least one texturized surface comprises a plurality of grooves on the at least one texturized surface. Lee210 teaches wherein the at least one texturized surface comprises a plurality of grooves on the at least one texturized surface (fig. 5). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Hashizume with that of Lee210 so that wherein the at least one texturized surface comprises a plurality of grooves on the at least one texturized surface to restrict flow of die attach adhesive and/or resin bleed from the die attach adhesive ([0010]). Regarding claim 7, Lee210 teaches wherein the plurality of grooves have a regular spacing or an irregular spacing (fig. 5). Regarding claim 9, Hashizume and Lee210 disclose all the limitations of claim 6 as discussed above on which this claim depends. Lee210 also discloses wherein at least one of the plurality of grooves extends to a depth of about 5 microns to about 50 microns ([0042]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Hashizume with that of Lee210 so that wherein at least one of the plurality of grooves extends to a depth of about 5 microns to about 50 microns to restrict flow of die attach adhesive and/or resin bleed from the die attach adhesive ([0010]). Regarding claim 10, Hashizume and Lee210 disclose all the limitations of claim 6 as discussed above on which this claim depends. Lee210 does not explicitly teach wherein at least one of the plurality of grooves extends to a depth of about 51 microns to about 100 microns, however, Lee210 teaches groove extends within a range of 1 μm to 50 μm ([0042]). So, it is obvious to one of ordinary skill in the art to determine the workable or optimal range such as a depth in the range about 51 microns to about 100 microns through routine experimentation and optimization to obtain optimal or desired performance. Since Applicant has not shown that these ranges are novel and that they would not have been found through routine experimentation, it would have been obvious to one having ordinary skill in the art to optimize these ranges in order to meet customer requirements and to obtain optimal or desired performance, and it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Hashizume with that of Lee210 so that wherein at least one of the plurality of grooves extends to a depth of about 51 microns to about 100 microns to restrict flow of die attach adhesive and/or resin bleed from the die attach adhesive ([0010]). Regarding claim 11, Lee210 teaches wherein the plurality of grooves has generally perpendicular sidewalls or angled sidewalls (fig. 5). Regarding claim 13, Hashizume discloses wherein the at least one texturized surface comprises a texturized pattern, wherein the texturized pattern is a repeated pattern across at least a portion of the texturized surface (fig. 7-8). Regarding claim 15, Hashizume discloses wherein the texturized pattern is a parallel line pattern, an orthogonal line pattern, a wave line pattern, a zig-zag line pattern (fig. 7-8), a grid line pattern, a crosshatch line pattern, a polygonal line pattern, a linear array of polygons, or a staggered array of polygons Claim 27 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Heng832, as applied to claim 1 above, and further in view of Manola et al. (US publication 2022/0108975 A1), hereinafter referred to as Manola975. Regarding claim 27, Heng832 discloses all the limitations of claim 1 as discussed above on which this claim depends. Heng832 does not explicitly teach wherein the one or more semiconductor die comprise silicon carbide. Manola975 teaches wherein the one or more semiconductor die comprise silicon carbide ([0012]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Heng832 with that of Manola975 so that wherein the one or more semiconductor die comprise silicon carbide of a wide bandgap semiconductor for enhanced electrical properties. Regarding claim 29, Heng832 discloses all the limitations of claim 1 as discussed above on which this claim depends. Heng832 does not explicitly teach wherein the one or more semiconductor die comprise a Group III-nitride. Manola975 teaches wherein the one or more semiconductor die comprise a Group III-nitride ([0012]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Heng832 with that of Manola975 so that wherein the one or more semiconductor die comprise a Group III-nitride of a wide bandgap semiconductor for enhanced electrical properties. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohammed R Alam whose telephone number is 469-295-9205 and can normally be reached between 8:00am-6:00pm (M-F) or by e-mail via Mohammed.Alam1@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMED R ALAM/Primary Examiner, Art Unit 2897
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Prosecution Timeline

Dec 15, 2023
Application Filed
May 20, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
95%
With Interview (+6.2%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 562 resolved cases by this examiner. Grant probability derived from career allowance rate.

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