Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested:
“Semiconductor devices including gate structures extending through upper portions of active patterns and bit line structures on central portions”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Cho (US 20150340453).
Regarding claim 1. Fig 2A of Cho discloses A semiconductor device 100A comprising:
an active pattern 11 on a substrate 10 [0032];
a gate structure 20 ([0036]: “gate structures 20”) extending through an upper portion (refer to the upper portion of 11d/11s) of the active pattern, the gate structure having an upper surface (top surface of 20) higher than an upper surface of the active pattern (due to the 31 between each upper surfaces);
a conductive filling pattern 40 including:
a lower portion (the bottommost portion of the 40 directly contacting 11s, which is between rounded corners) on the active pattern, the lower portion contacting an upper sidewall of the gate structure (contacting upper sidewall of 20); and
an upper portion (the upper portion of the 40 between 32) on the lower portion, the upper portion having a width (the width of the 40 between 32) greater than a width (the width of the 40 below 31) of the lower portion (Fig 1: due to rounded corners of the lower portion); and
a bit line structure 50 [0036] on the conductive filling pattern.
Regarding claim 2. Cho discloses The semiconductor device according to claim 1, wherein the gate structure extends in a first direction (Fig 1B: Y) substantially parallel to an upper surface of the substrate (Fig 1B), and the bit line structure extends in a second direction (Fig 1B: X) substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction (Fig 1B), and
wherein a width in the second direction of the upper portion of the conductive filling pattern is greater than a width in the second direction of the lower portion of the conductive filling pattern (Fig 2: due to rounded corner shape of the lower portion).
Regarding claim 3. Cho discloses The semiconductor device according to claim 2, wherein:
the active pattern extends in a fourth direction (Fig 1B: Z) substantially parallel to the upper surface of the substrate and having an acute angle with respect to each of the first and second directions (Fig 1B: Y-Z and Z-X, which are acute angle because Y-X is right angle and Z is inside the right angle),
the gate structure is one of two gate structures (Fig 2A: left and right 20), the two gate structures extending through two parts, respectively, of the active pattern spaced apart from each other in the fourth direction (Fig 1B/Fig 2A), and
the lower portion of the conductive filling pattern commonly contacts upper sidewalls of the two gate structures, the upper sidewalls facing each other (Fig 2A).
Regarding claim 4. Cho discloses The semiconductor device according to claim 3, wherein the active pattern is one of a plurality of active patterns (three fins of active patterns in 11) spaced apart from each other in the first direction (Fig 2A), and end portions of the plurality of active patterns in the fourth direction are aligned with each other in the first direction (Fig 1B/Fig 2A).
Regarding claim 5. Cho discloses The semiconductor device according to claim 1, wherein the gate structure includes a gate electrode 24 [0038], a capping pattern 27 [0038] and a gate insulation pattern 22 [0038], the gate electrode and the capping pattern being sequentially stacked in a vertical direction substantially perpendicular to the upper surface of the substrate, and the gate insulation pattern being disposed on sidewalls of the gate electrode and the capping pattern (Fig 2A), and
wherein the lower portion of the conductive filling pattern contacts a sidewall of the capping pattern (Fig 2A).
Regarding claim 6. Cho discloses The semiconductor device according to claim 5, wherein the upper portion of the conductive filling pattern contacts a portion of an upper surface of the capping pattern (Fig 2A; also refer to Fig 3J, the one of top corners of 27 contacts the lateral surface of 40).
Regarding claim 7. Cho discloses The semiconductor device according to claim 1, further comprising:
a first pad 31 on the active pattern (Fig 2A); and
a second pad 32 on the first pad (Fig 2A),
wherein the lower portion of the conductive filling pattern extends through the first pad, and the upper portion of the conductive filling pattern extends through the second pad (Fig 2A).
Regarding claim 8. Cho discloses The semiconductor device according to claim 7, wherein the first pad includes an oxide ([0051]: 31 may include silicon oxide), and the second pad includes a nitride ([0052]: 32 may include silicon nitride).
Regarding claim 9. Cho discloses The semiconductor device according to claim 1, further comprising an ohmic contact pattern 54 between the conductive filling pattern and the active pattern (Fig 2A), the ohmic contact pattern including a metal silicide ([0053]: TiSi).
Regarding claim 10. Fig 1B and Fig 3L (sectional view of Fig 1B along the line II-II’) of Cho disclose A semiconductor device comprising:
an active pattern 11 on a substrate 10 [0032];
first 12b (which is located on lateral surface and bottom surface of the active pattern 11) and second 31 (located on top of the first pad) pads stacked on the active pattern in a vertical direction substantially perpendicular to an upper surface of the substrate (Fig 3L);
a gate structure 20 [0036] extending through an upper portion of the active pattern and the first and second pads (Fig 3L: the 12b and 31 surrounding the 20, and the top surface of 20 coplanar with the top surface of 31, thus the 20 extending through 12b and 31);
a conductive filling pattern 40 extending through portions of the upper portion of the active pattern and the first and second pads that are adjacent to the gate structure (Fig 3L); and
a bit line structure 50 on the conductive filling pattern;
wherein the gate structure includes a gate electrode 24, a capping pattern 27 and a gate insulation pattern 22, the gate electrode and the capping pattern being stacked in the vertical direction, and the gate insulation pattern being disposed on sidewalls of the gate electrode and the capping pattern (Fig 3L); and
wherein a top surface (Fig 3L: the top surface of 22 contacting the bottom surface of 32) of the gate insulation pattern is substantially coplanar with an upper surface (the upper surface of 40 between 31) of the conductive filling pattern (Fig 3L: they are coplanar along the bottom surface of 32).
Regarding claim 11. Cho discloses The semiconductor device of claim 10, wherein the top surface of the gate insulation pattern is substantially coplanar with an upper surface of the second pad (Fig 3L: the top surface of 22 is coplanar with the upper surface of 31 along the bottom surface of 32).
Regarding claim 12. Cho discloses The semiconductor device of claim 10, wherein an impurity region doped ([0132]: 11d and 11s) with impurities is formed at an upper portion of the active pattern (Fig 3L), and
wherein a lower surface of the conductive filling pattern is lower than an upper surface of the impurity region (Fig 3L: because the bottom surface of 40 is deeper than the top surface of 11d/11s).
Regarding claim 13. Cho discloses The semiconductor device according to claim 10, wherein the conductive filling pattern contacts the sidewall of the capping pattern (Fig 3L).
Regarding claim 14. Cho discloses The semiconductor device according to claim 10, wherein the conductive filling pattern contacts a sidewall of the gate insulation pattern (Fig 3L: the bottom portion of 40 contacting the upper sidewall portion of 22).
Regarding claim 15. Cho discloses The semiconductor device according to claim 10, further comprising a spacer 32 between and contacting a sidewall of the conductive filling pattern and the sidewall of the capping pattern (Fig 3L: the right bottom corner 32 of left side 32 is between and contacting left portion of 40 and the right sidewall corner of 27; and the left bottom corner 32 of the right side 32 is between and contacting right portion of 40 and the left sidewall corner of 27).
Regarding claim 16. Cho discloses The semiconductor device according to claim 10, wherein:
the gate structure extends in a first direction (Fig 1B: Y) substantially parallel to the upper surface of the substrate, and the bit line structure extends in a second direction (Fig 1B: X) substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction (Fig 1B),
the active pattern extends in a fourth direction (Fig 1B: Z) substantially parallel to the upper surface of the substrate and having an acute angle with respect to each of the first and second directions (Fig 1B: Y-Z and Z-X, which are acute angle because Y-X is right angle and Z is inside the right angle),
the gate structure is one of two gate structures (Fig 3L: left and right 20), the two gate structures extending through two parts, respectively, of the active pattern spaced apart from each other in the fourth direction (Fig 1B/Fig 3L), and
the conductive filling pattern is disposed between upper sidewalls of the two gate structures, the upper sidewalls facing each other (Fig 3L).
Regarding claim 17. Fig 1B and Fig 2A (sectional view of Fig 1B along the line II-II’) of Cho disclose A semiconductor device 100A comprising:
active patterns 11 (Fig 2A: the three fins surrounded by 12) on a substrate 10 [0032];
an isolation structure 12 on the substrate, the isolation structure covering sidewalls of the active patterns (Fig 2A);
first 31 and second 32 pads stacked on the active patterns and the isolation structure in a vertical direction substantially perpendicular to an upper surface of the substrate (Fig 2A: because 31/32 are vertically stacked);
gate structures 20 each extending through upper portions of the active patterns and the isolation structure (Fig 2A), and
the first and second pads in a first direction (Fig 1B: Y) substantially parallel to the upper surface of the substrate (Fig 1B/Fig 2A);
conductive filling patterns 40, each of the conductive filling patterns being disposed on a central portion (Fig 2A: the portion near 11s) of a corresponding one of the active patterns (Fig 2A) and the isolation structure and extending through the first and second pads (Fig 2A);
bit line structures 50 on the conductive filling patterns and the second pad (Fig 2A), each of the bit line structures extending in a second direction (Fig 1B: X) substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction (Fig 1B);
contact plug structures 60 [0032] on opposite end portions (Fig 2A), respectively, of the active patterns; and
capacitors 80 [0036] on the contact plug structures, respectively (Fig 2A),
wherein each of the conductive filling patterns includes:
a lower portion (Fig 2A: the lower portion of 40 below 32) extending through the first pad and contacting upper sidewalls of the gate structures (Fig 2A), the first pad having a first width in the second direction (Fig 2A: the width of 40 between rounded corners); and
an upper portion (the upper portion of 40 between 32) on the lower portion, the upper portion having a second width (the width of 40 between 32) in the second direction greater than the first width in the second direction (Fig 2A: due to the rounded corners of 40 in the bottom portion).
Regarding claim 18. Cho discloses The semiconductor device according to claim 17, wherein each of the active patterns extends in a fourth direction (Fig 1B: Z) substantially parallel to the upper surface of the substrate and having an acute angle with respect to each of the first and second directions (Fig 1B), and
wherein the active patterns are spaced apart from each other in the first direction, and end portions of the active patterns in the fourth direction are aligned with each other in the first direction (Fig 1B/Fig 2A).
Regarding claim 19. Cho discloses The semiconductor device according to claim 18, wherein two gate structures among the gate structures that are spaced apart from each other in the second direction extend through an upper portion of each of the active patterns (Fig 2A); and
wherein the lower portion of each of the conductive filling patterns commonly contacts upper sidewalls of the two gate structures, the upper sidewalls facing each other (Fig 2A).
Regarding claim 20. Cho discloses The semiconductor device according to claim 17, wherein each of the gate structures includes a gate electrode 24 and a capping pattern 27 stacked in the vertical direction, and a gate insulation pattern disposed on sidewalls of the gate electrode and the capping pattern (Fig 2A), and
wherein the lower portion of each of the conductive filling patterns contacts a sidewall of the capping pattern (Fig 2A).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Changhyun Yi/Primary Examiner, Art Unit 2812