Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Elections/Restrictions
Applicant’s elections without traverse of Invention I and Species A and C (Claims 1-7, 9-10 and 12-16) in the reply filed on 04/16/2026 are acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/21/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being unpatentable over US10008583B1; Rodder et al.; (hereinafter “Rodder”).
Regarding Claim 1, Rodder teaches a gate all around (GAA) transistor (#100, Figure 1) comprising:
a gate (#107) having opposing sides;
a gate spacer (#109) on the opposing sides of the gate;
one or more inner spacers (#110-113) below and vertically aligned with the gate spacers (#109);
a source/drain material (#101-102/#115-117) on either side of the gate (#107) and extending under the inner spacers (#110-113); and
a channel layer (#106) under the gate (#107), extending under the inner spacer (#112) and in contact with the source/drain material (#115-117);
wherein the channel layer has a first germanium concentration and wherein the source/drain material has a second germanium concentration (col. 8, ln. 4-9, source/drain material has higher Ge concentration than channel layers).
Claims 12-13 and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over US20220115498A1; Chu et al.; (hereinafter “Chu”)
Regarding Claim 12, Chu teaches a gate all around transistor (#20N-P, Figure 1) comprising:
a gate (#290) having opposing sides;
a gate spacer (#41) on the opposing sides of the gate (#290);
an inner spacer (#74) below and vertically aligned with the gate spacers (#41);
a source/drain material (#82) on either side of the gate (#290);
a cladded channel layer ([0020], low-concentration SiGe layers #242-243 on topsides and undersides of silicon nanosheets #225A-C) under the gate (#290), extending under the inner spacer (#74) wherein a cladding material of the cladded channel is in contact with the source/drain material (Figure 9D-F, low-concentration SiGe layers #222A-C/#224A-C contact outer sidewalls of spacer #75 which also contact source/drain #82 according to [0062]; and
wherein the source/drain material (#82, [0017]) and the cladding material comprise silicon germanium (low-concentration SiGe layers #242-243).
Regarding Claim 13, Chu teaches the gate all around transistor as described in claim 12, wherein Chu further teaches the source/drain material has a second germanium concentration ([0065]), and the cladding material has a first germanium concentration ([0021] or [0054]).
Regarding Claim 15, Chu teaches the gate all around transistor as described in claim 13, wherein Chu further teaches the first germanium concentration is in the range of 15% to 50% germanium ([0021] or [0054], the low concentration SiGe layers has a Ge concentration such as 10-25%).
Regarding Claim 16, Chu teaches the gate all around transistor as described in claim 13, wherein Chu further teaches a core material of the cladded channel layer wherein the core material includes silicon ([0020], silicon nanosheet #225A-C).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-3 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Rodder in view of US20250081520A1; Cheng et al.; (hereinafter “Cheng”).
Regarding Claim 2, Rodder teaches the gate all around transistor as described in claim 1.
Rodder does not explicitly teach the second germanium concentration is in a range of 20% to 70% germanium.
However, Cheng teaches a GAA transistor ([0011]), wherein the second germanium concentration is in a range of 20% to 70% germanium ([0082], source/drain layer has Ge concentration between 20-70%).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to have modified Rodder with the ranges disclosed by Cheng for the benefits of SiGe source/drain material in GAA device such as inducing compressive strain in the channel region to prevent strain loss and reduce channel resistance, and improving device performance according to Cheng, [0013] or [0125].
Regarding Claim 3, Rodder in view of Cheng teaches the gate all around transistor as described in claim 2, wherein Rodder further teaches the first geranium concentration is less than the second germanium concentration (col. 8, ln. 4-9, source/drain material has higher Ge concentration than channel layers).
Regarding Claim 9, Rodder teaches the gate all around transistor as described in claim 1.
Rodder does not explicitly teach the gate extends under the inner space.
However, Cheng teaches the gate extends under the inner spacer (Figure 1A, gate structure #50 includes a portion under inner spacers #32).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Rodder with the teaching of Cheng, as it would be a simple substitution of one known element (inner spacer of Rodder) for another (inner spacer of Cheng) in comparable structures to obtain predictable results. See MPEP 2143(I)(B).
Regarding Claim 10, Rodder in view of Cheng teaches the gate all around transistor as described in claim 9.
Rodder does not explicitly teach the inner spacer has a length and wherein the gate extends under the inner spacer by a distance less than or equal to half of the inner spacer length.
However, Cheng teaches the inner spacer has a length and wherein the gate extends under the inner spacer by a distance less than or equal to half of the inner spacer length (Figure 1A, gate structure #50 includes a portion under inner spacers #32 which is smaller than a length of the spacer).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Rodder with the teaching of Cheng for reason set forth in rejection of claim 9.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Rodder in view of Cheng, and further in view of Chu.
Regarding Claim 4, Rodder in view of Cheng teaches the gate all around transistor as described in claim 2.
Rodder does not explicitly teach the first germanium concentration is equal to or less than 75% of the second geranium concentration.
However, Chu teaches the first germanium concentration is equal to or less than 75% of the second geranium concentration ([0054], the low concentration SiGe layer of the nanosheet has a Ge concentration such as 10% or lower).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to have selected the overlapping portion of the ranges disclosed by Chu because selection of overlapping portion of ranges has been held to be a prima facie case of obviousness. Additionally, a lower Ge concentration in the channel layer can prevent undesirable shift in device threshold voltage according to Chu, [0054].
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Rodder in view of Chu.
Regarding Claim 5, Rodder teaches the gate all around transistor as described in claim 1.
Rodder does not explicitly teach the channel layer comprises a silicon core and a silicon germanium cladding layer.
However, Chu teaches the channel layer comprises a silicon core and a silicon germanium cladding layer ([0020], low-concentration SiGe layers #242-243 on topsides and undersides of silicon nanosheets #225A-C).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Rodder with the teaching of Chu in order to shift device threshold voltage in the positive voltage direction according to Chu, [0020].
Regarding Claim 6, Rodder in view of Chu teaches the gate all around transistor as described in claim 5.
Rodder does not explicitly teach the cladding layer is in direct contact with the source/drain material.
However, Chu teaches the cladding layer is in direct contact with the source/drain material (Figure 9D-F, low-concentration SiGe layers #222A-C/#224A-C contact outer sidewalls of spacer #75 which also contact source/drain #82 according to [0062]).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Rodder with the teaching of Chu for reason set forth in rejection of claim 5.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Rodder in view of US20180082902A1; Balakrishnan et al.; (hereinafter “Balakrishnan”).
Regarding Claim 7, Rodder teaches the gate all around transistor as described in claim 1.
Rodder does not explicitly teach the inner spacer has a length and wherein the source/drain material extends under the inner spacer by a distance less than or equal to half of the inner spacer length.
However, Balakrishnan teaches a nanosheet transistor ([0005]), wherein the inner spacer has a length and wherein the source/drain material extends under the inner spacer by a distance less than or equal to half of the inner spacer length (Figure 10, [0077], a portion of channel #140 under dielectric layer #180, [0070], is recessed before forming source/drain material in the recess).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Rodder with the teaching of Balakrishnan in order to provide the transistor device with longer nanosheet channel layers after recessing that produces lower leakage current according to Balakrishnan, [0086].
Claims 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chu in view of Cheng.
Regarding Claim 14, Chu teaches the gate all around transistor as described in claim 13.
Chu does not explicitly teach the second germanium concentration is in a range of 20% to 70% germanium.
However, Cheng teaches the second germanium concentration is in a range of 20% to 70% germanium ([0082], source/drain layer has Ge concentration between 20-70%).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to have modified Chu with the ranges disclosed by Cheng for the benefits of SiGe source/drain material in GAA device such as inducing compressive strain in the channel region to prevent strain loss and reduce channel resistance, and improving device performance according to Cheng, [0013] or [0125].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US2050151335A1 – Figures 2-3
US20240421191A1 – Figure 1
US20220320276A1 – Figure 15
US20210328013A1 – Figures 10-11
US20190181224A1 – Figure 8
US20190035913A1 – Figure 16
US10714392B2 – Figures 9-23
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/TIEN TRAN/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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