Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species A, reading on claims 1-19, 13-20 in the reply filed on 07/20/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Claim 19 recites in last paragraph “wherein the second device region comprises a second substrate comprising a passive device therein and having a thickness smaller than a thickness of the first substrate in a direction perpendicular to an upper surface of the first substrate”. However, none of the figures show this claimed feature.
Fig. 3 and related par. [0044-0045] of the instant application describe:
[0044] The second device region 200 on a side opposite the first device region 100 with respect to the upper surface of the first bonding structure 130 may include the second substrate 210 including a passive device 212 therein.
[0045] In various embodiments, a thickness d1 of the first substrate 110 may be less than a thickness d2 of the second substrate 210 in the second direction (y direction) perpendicular to the upper surface of the first substrate 110.
However, claim 19 recites d2<d1, which is neither shown in the drawings nor described in the original disclosure.
Therefore, the above cited must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 19-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 19 recites in last paragraph “wherein the second device region comprises a second substrate comprising a passive device therein and having a thickness smaller than a thickness of the first substrate in a direction perpendicular to an upper surface of the first substrate”.
Fig. 3 and related par. [0044-0045] of the instant application describe:
[0044] The second device region 200 on a side opposite the first device region 100 with respect to the upper surface of the first bonding structure 130 may include the second substrate 210 including a passive device 212 therein.
[0045] In various embodiments, a thickness d1 of the first substrate 110 may be less than a thickness d2 of the second substrate 210 in the second direction (y direction) perpendicular to the upper surface of the first substrate 110.
However, claim 19 recites d2<d1, which is not described in the original disclosure, failing to comply with the written description requirement and rejected under 112(a).
Claim 20 does not cure the deficiency and likewise rejected under this section.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites “a first bonding pad buried in the first bonding layer and having an exposed upper surface” in line 4. Thereafter, recites “an upper surface of the first bonding layer and an upper surface of the first bonding pad are coplanar” in lines 6-7. It is unclear if “an upper surface of the first bonding pad” cited in lines 6-7 is referring to the “exposed upper surface” of the first bonding pad cited in line 4. For the purposes of examination, they will be interpreted as same upper surface.
Claims 4-6 do not cure the deficiency and likewise rejected under this section.
Claim 5 recites “wherein the first bonding structure includes: a first bonding layer including an insulating material” in lines 2-3. However, claim 5 depends on claim 3 and claim 3 recites “wherein the first bonding structure includes a first bonding layer including an insulating material” in lines 1-3. Therefore, it is unclear if “a first bonding layer” in claims 3 and 5 are the same first bonding layer or a different one. For the purposes of examination, they will be interpreted as same first bonding layer.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-6, 9, 13-16, 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shen et al. (US 20220285434 A1; hereinafter “Shen”).
In re claim 1, Shen discloses in figs. 1-2, 5, an integrated circuit device comprising:
a first substrate 210 (¶33) having a first surface (e.g., an upper surface S1) and a second surface (e.g., a lower surface S2) opposite to the first surface, and including an active device D2 therein (¶34);
a first back end of layer (BEOL) structure 220 (fig. 2B; ¶35) on the first surface of the first substrate S1 and configured to route signals (¶38, 49; “The peripheral circuit 220 may have function for detecting states in the memory cells MC of the memory die 100, controlling the memory cells MC of the memory die 100, and input/output operations. Thus, the peripheral circuit 220 may operate the memory cells (such as the memory cells MC) once the peripheral circuit 220 is electrically connected to the memory cells”);
a second substrate (a second substrate comprising 110, and layers 122-0 through 122-6; hereinafter “Subx2”) (fig. 1D; ¶19) on the first surface of the first substrate S1 with the first BEOL structure 220 therebetween, and comprising a passive device MC (e.g., a magnetic tunnel junction (MTJ) memory cell; ¶19, 23) therein;
a power distribution structure 300 on the second surface of the first substrate S2 (fig. 5; ¶30);
a first bonding structure (246, 250A-250C) on the first BEOL structure 220 (¶39-40); and
a second bonding structure (146, 150A-150C) between the first bonding structure (246, 250A-250C) and the second substrate Subx2 (¶27-28),
wherein an upper surface of the second bonding structure (146, 150A-150C) contacts an upper surface of the first bonding structure (246, 250A-250C) to form an interface with the first bonding structure, and
the second bonding structure (146, 150A-150C) and the first bonding structure (246, 250A-250C) are positioned between the first substrate 210 and the second substrate Subx2.
In re claim 3, Shen discloses in figs. 1-2, 5, the integrated circuit device of claim 1,
wherein the first bonding structure includes a first bonding layer 246 including an insulating material (¶39); and a first bonding pad 252b (¶41) buried in the first bonding layer 246 and having an exposed upper surface, and an upper surface of the first bonding layer 246 and an upper surface of the first bonding pad 252b are coplanar (fig. 2D).
In re claim 4, Shen discloses in figs. 1-2, 5, the integrated circuit device of claim 3, further comprising: a second BEOL structure (a second BEOL structure comprising 122-7, 124-5, 126-5; hereinafter “BEOL2”) (¶19) between the second substrate Subx2 and the second bonding structure (146, 150A-150C) and configured to route signals (¶19, 24).
In re claim 5, Shen discloses in figs. 1-2, 5, the integrated circuit device of claim 4, wherein the first bonding structure includes a first bonding layer 246 including an insulating material (¶39) (as best understood); and
a first via 252a (¶41) passing through the first bonding layer 246 and connected to the first BEOL structure 220,
the second bonding structure includes, a second bonding layer 146 including an insulating material (¶27); and
a second via 152a passing through the second bonding layer 146 and connected to the second BEOL structure BEOL2, and
the first via 252a and the second via 152a vertically overlap each other.
In re claim 6, Shen discloses in figs. 1-2, 5, the integrated circuit device of claim 4, further comprising:
a signal pad (signal pad comprising 250, 252, 304) (¶47, 49) on the second surface of the first substrate S2, wherein the signal pad (250, 252, 304) is connected to the passive device MC through the first BEOL structure 220 and the second BEOL structure BEOL2.
In re claim 9, Shen discloses in figs. 1-2, 5, the integrated circuit device of claim 1, further comprising: a power pad (signal pad comprising 250, 252, 304) (¶47, 49) on the second surface of the first substrate S2, wherein the power pad is configured to supply power to the active device (“The circuit structure 300 may provide the power supply and the power supply network connecting to the power supply for the memory die 100 and the peripheral circuit die 200”; ¶49).
In re claim 13, Shen discloses in figs. 1-2, 5, an integrated circuit device comprising:
a first bonding structure (246, 250B) (¶39-40);
a second bonding structure (146, 150B) (¶27-28) contacting an upper surface of the first bonding structure (an upper surface of 246, 250A-250C; hereinafter “Bond_S1”) to form an interface;
a first device region 210, 220 defined in one direction (e.g., vertically down direction; hereinafter “ZD”) with respect to the upper surface (Bond_S1); and
a second device region (a second device region comprising 110, and layers 122-0 through 122-6; hereinafter “Device_R2”) (fig. 1D; ¶19) defined in a direction (e.g., vertically up direction; hereinafter “ZU”) opposite to the one direction ZD with respect to the upper surface (Bond_S1),
wherein the first device region comprises:
a first substrate 210 having a first surface (e.g., an upper surface S1) and a second surface (e.g., a lower surface S2) opposite to the first surface, and comprising an active device D2 therein (¶33-33);
a first back end of layer (BEOL) 220 (fig. 2B; ¶35) on the first surface of the first substrate S1 and configured to route signals (¶38, 49; “The peripheral circuit 220 may have function for detecting states in the memory cells MC of the memory die 100, controlling the memory cells MC of the memory die 100, and input/output operations. Thus, the peripheral circuit 220 may operate the memory cells (such as the memory cells MC) once the peripheral circuit 220 is electrically connected to the memory cells”);
a power distribution structure 300 on the second surface of the first substrate S2 (fig. 5; ¶30); and
a through via (a through via comprising a left through via, TV and all the conductors connected to the left TV including 250A, 150A. Hereinafter “TSV”) passing through the first device region 210, 220 and the second bonding structure (146, 150B) and configured to transfer an electrical signal to the second device region (Device_R2) (¶49),
wherein the second device region (Device_R2) comprises a second substrate 110, 120 comprising a passive device MC (e.g., a magnetic tunnel junction (MTJ) memory cell; ¶19, 23), and the first substrate 210 does not comprise the passive device.
In re claim 14, Shen discloses in figs. 1-2, 5, the integrated circuit device of claim 13, wherein the second device region (Device_R2) further comprises a second BEOL structure (a second BEOL structure comprising 122-7, 124-5, 126-5; hereinafter “BEOL2”) (¶19) between the second substrate 110, 120 and the second bonding structure (146, 150B) and configured to route signals (¶19, 24).
In re claim 15, Shen discloses in figs. 1-2, 5, the integrated circuit device of claim 13, wherein the first bonding structure includes a first bonding layer 246 including an insulating material (¶39); and
a first via 252a (¶41) passing through the first bonding layer 246 and connected to the first BEOL structure 220.
In re claim 16, Shen discloses in figs. 1-2, 5, the integrated circuit device of claim 15, wherein a length of the through via (TSV) is longer than a length of the first via 252a in a direction perpendicular to the first surface S1.
In re claim 18, Shen discloses in figs. 1-2, 5, the integrated circuit device of claim 13, wherein a length of the through via (TSV) is longer than a length of the first BEOL structure 220 in a direction perpendicular to the first surface S1.
Claim(s) 1, 7, 13 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lu et al. (US 20240063160 A1; hereinafter “Lu”).
In re claim 1, Lu discloses in figs. 1A-1D, an integrated circuit device comprising a first substrate 103b (¶22) having a first surface (e.g., a lower surface in fig. 1D; hereinafter “S1”) and a second surface (e.g., an upper surface in fig. 1D; hereinafter “S2”) opposite to the first surface S1, and including an active device 121b (e.g., a gate-all-around (GAA) transistor; ¶25) therein;
a first back end of layer (BEOL) structure 122b on the first surface of the first substrate S1 and configured to route signals (¶22, 24; a first back end of layer (BEOL) structure 122b are interconnect layers that are connected to the third interconnect wirings 124 and route signals from the power delivery from outer systems);
a second substrate 103a (¶33) on the first surface of the first substrate S1 with the first BEOL structure 122b therebetween, and comprising a passive device 121a (e.g., resistors; ¶19) therein;
a power distribution structure (e.g., power distribution network (PDN) circuitry; ¶24) on the second surface of the first substrate S2;
a first bonding structure (125b, 126b) (¶22) on the first BEOL structure 122b; and
a second bonding structure (125a, 126a) (¶35) between the first bonding structure (125b, 126b) and the second substrate 103a,
wherein an upper surface of the second bonding structure (125a, 126a) contacts an upper surface of the first bonding structure (125b, 126b) to form an interface with the first bonding structure (125b, 126b), and
the second bonding structure (125a, 126a) and the first bonding structure (125b, 126b) are positioned between the first substrate 103b and the second substrate 103a.
In re claim 7, Lu discloses in figs. 1-2, 5, the integrated circuit device of claim 1, wherein the passive device 121a includes at least one of a vertical PNP transistor, a diode, a capacitor, an inductor, a resistor (e.g., resistors; ¶19), an electrostatic discharge (ESD) device, an eFuse, or a one-time programmable (OTP) memory device.
In re claim 13, Lu discloses in figs. 1A-1D, an integrated circuit device comprising:
a first bonding structure (112b, and middle section of the connectors 125b, 126b) (¶22);
a second bonding structure (112a, and middle section of the connectors 125a, 126a) (¶35) contacting an upper surface of the first bonding structure (e.g., in an upside-down view of fig. 1D; an upper surface of 125b, 126b) to form an interface (e.g., an interface between 104a, 104b);
a first device region 103b (¶22) defined in one direction (e.g., vertically up direction; hereinafter “+Z”) with respect to the upper surface; and
a second device region 103a (¶18-20) defined in a direction (e.g., -Z) opposite to the one direction with respect to the upper surface,
wherein the first device region 103b comprises:
a first substrate 111b having a first surface and a second surface opposite to the first surface, and comprising an active device 121b (e.g., a gate-all-around (GAA) transistor; ¶25) therein;
a first back end of layer (BEOL) structure 122b on the first surface of the first substrate S1 and configured to route signals (¶22, 24; a first back end of layer (BEOL) structure 122b are interconnect layers that are connected to the third interconnect wirings 124 and route signals from the power delivery from outer systems);
a power distribution structure (e.g., power distribution network (PDN) circuitry; ¶24) on the second surface of the first substrate S2; and
a through via (a through via comprising connectors 124, left section of the connectors 122b, 125b, 126b, 126a, 125a, 112a. Claim 13 in its current form does not claim any shape of material for the through via to distinguish over the prior art) passing through the first device region 103b and the second bonding structure 112a and configured to transfer an electrical signal to the second device region 103a,
wherein the second device region 103a comprises a second substrate 111a comprising a passive device (¶18-20), and the first substrate 111b does not comprise the passive device.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 8 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu, as applied to claim 1 above.
In re claim 2, Lu discloses in figs. 1A-1D, the integrated circuit device of claim 1, the first substrate 103b does not include the passive device (¶25).
Lu further discloses wherein the second substrate 103a is a bulk substrate (¶20) and a thickness (T2) of first semiconductor substrate 103b may be reduced to less than about 0.5 um or 0.1 um (¶25). Lu also discloses the components in first device region 121b may have small thickness and/or may have portions above silicon substrate, so the first semiconductor substrate 103b can be thinner (¶25).
Based on Lu’s teachings, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to make a thickness of the first substrate 103b less than a thickness of the second substrate 103a in a direction perpendicular to an upper surface of the first substrate S1 such that the power and ground signals can be provided to the device regions 121b along a shorter path from the back side of the substrate 103b (¶24 of Lu).
In re claim 8, in an alternative interpretation of Lu’s disclosed figs. 1A-1D, the integrated circuit device of claim 1, a first BEOL structure can be interpreted as the first interconnect layer 122b directly connected to the device 121a and a bonding structure can be interpreted as entire thickness of 104b except the first BEOL. In this interpretation, a thickness of the first substrate T2 is about 0.5 um or 0.1 um (¶25) and a thickness of the first bonding structure (~T3) is about 0.5 μm to about 3 um (¶24).
Based on Lu’s teachings, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to make a thickness of the first substrate less than a thickness of the first bonding structure such that the power and ground signals can be provided to the device regions 121b along a shorter path from the back side of the substrate and also the signal interaction latency and the energy loss between device 121a and 121b may be reduced (¶24 of Lu).
In re claim 17, Lu discloses in figs. 1A-1D, the integrated circuit device of claim 13, the first substrate 103b does not include the passive device (¶25).
Lu further discloses wherein the second substrate 103a is a bulk substrate (¶20) and a thickness (T2) of first semiconductor substrate 103b may be reduced to less than about 0.5 um or 0.1 um (¶25). Lu also discloses the components in first device region 121b may have small thickness and/or may have portions above silicon substrate, so the first semiconductor substrate 103b can be thinner (¶25).
Based on Lu’s teachings, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to make a thickness of the first substrate 103b less than a thickness of the second substrate 103a in a direction perpendicular to an upper surface of the first substrate S1 such that the power and ground signals can be provided to the device regions 121b along a shorter path from the back side of the substrate 103b (¶24 of Lu).
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shen et al. (US 20220285434 A1; hereinafter “Shen”) in view of Liu et al. (US 20240006311 A1; hereinafter “Liu”).
In re claim 19, Shen discloses in figs. 1-2, 5, an integrated circuit device comprising:
a first bonding structure (246, 250B) (¶39-40);
a second bonding structure (146, 150B) (¶27-28) contacting an upper surface of the first bonding structure (an upper surface of 246, 250A-250C; hereinafter “Bond_S1”) to form an interface;
a first device region 210, 220 defined in one direction (e.g., vertically down direction; hereinafter “ZD”) with respect to the upper surface (Bond_S1); and
a second device region (a second device region comprising 110, and layers 122-0 through 122-6; hereinafter “Device_R2”) (fig. 1D; ¶19) defined in a direction (e.g., vertically up direction; hereinafter “ZU”) opposite to the one direction ZD with respect to the upper surface (Bond_S1),
wherein the first device region comprises:
a first substrate 210 having a first surface (e.g., an upper surface S1) and a second surface (e.g., a lower surface S2) opposite to the first surface, and comprising an active device D2 therein (¶33-33);
a first back end of layer (BEOL) 220 (fig. 2B; ¶35) on the first surface of the first substrate S1 and configured to route signals received from or transferred to the active device D2, and comprising first BEOL distribution patterns (224-1 through 224-5) having different vertical levels and first BEOL vias (226-2 through 226-5) between the first BEOL distribution patterns (¶35, 38, 49; “The peripheral circuit 220 may have function for detecting states in the memory cells MC of the memory die 100, controlling the memory cells MC of the memory die 100, and input/output operations. Thus, the peripheral circuit 220 may operate the memory cells (such as the memory cells MC) once the peripheral circuit 220 is electrically connected to the memory cells”);
a power distribution structure 300 on the second surface of the first substrate S2 and configured to supply power to the active device D2, comprising power distribution patterns 304 having different vertical levels, and power distribution vias between the power distribution patterns (“The conductive patterns 304 may route electrical signals such as by using vias and/or traces.”; ¶49); and
a power pad below the power distribution structure 300 (“The conductive patterns 304 may include bonding pads at the outermost surface of the circuit structure 300”; ¶49) and configured to supply power to the active device D2 (¶49),
wherein the second device region (Device_R2) comprises a second substrate 110, 120 comprising a passive device MC (e.g., a magnetic tunnel junction (MTJ) memory cell; ¶19, 23) therein.
Shen does not expressly disclose the second substrate comprising a passive device having a thickness smaller than a thickness of the first substrate in a direction perpendicular to an upper surface of the first substrate.
In the same field of endeavor, Liu discloses in fig. 10, an integrated circuit device wherein a second substrate 10 comprising a passive device 14 (¶13) having a thickness smaller than a thickness of a first substrate 20 in a direction perpendicular to an upper surface of the first substrate (¶39, 51).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Liu into the device of Shen in order to integrate different types of devices in a package structure with reduced product size (¶24 of Liu).
In re claim 20, Shen, as modified by Liu, discloses the integrated circuit device of claim 19 outlined above.
Shen further discloses in figs. 1-2, 5, the integrated circuit device of claim 19,
wherein the first bonding structure includes a first bonding layer 246 including an insulating material (¶39); and
a first bonding pad 252b (¶41) buried in the first bonding layer 246 and having an exposed upper surface,
wherein the second bonding structure includes a second bonding layer 146 including an insulating material (¶17); and
a second bonding pad 152b buried in the second bonding layer 146 and having an exposed upper surface, and
an upper surface of the first bonding layer 246 and an upper surface of the first bonding pad 252b are coplanar, and
an upper surface of the second bonding layer 146 and an upper surface of the second bonding pad 152b are coplanar.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wu et al. (US 20210217716 A1) discloses in figs. 6A-6B, an integrated circuit device comprising two dies 800, 900 directly bonded with each other. One of the first semiconductor die 800 and the second semiconductor die 900 can comprise a memory die. In this case, the memory die may include a three-dimensional memory device including a three-dimensional array of memory elements. Another of the first semiconductor die 800 and the second semiconductor die 900 can comprise a logic die including a control circuit for controlling operation of memory elements within the memory die. For example, the control circuit may include a bit line control circuit, a word line control circuit, a sensing circuit, a power supply circuit, a peripheral circuit, and/or input/output circuit. (¶81).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NILUFA RAHIM/Primary Examiner, Art Unit 2893
Prosecution Insights