Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election with traverse of Species B, reading on claims 1-7, 9-16, 18-20, in the reply filed on 07/08/2026 is acknowledged.
Claims 8 and 17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 07/08/2026.
The traversal is on ground that the identified embodiments do not impart a serious search or examination burden. MPEP §§ 803 and 808.02 require that a restriction requirement be supported by a showing of a serious search and/or examination burden, and not merely a difference in claim scope. The Restriction Requirement states that the "distinct species describe completely different devices with different structural design, effect, and utility" and "would require separate classification and text search" without identifying any specific differing field of search, or prior art unique to the species.
Examiner disagrees with the arguments presented above. As explained in the restriction requirement, in Species A, wherein a top surface of the upper pad 16 is in contact with a bottom surface of the lower pad 25, wherein the interposer does not include a redistribution insulating layer 141 including a photosensitive insulating material. In Species B, wherein a top surface of the upper pad 16 is in contact with a bottom surface of the lower pad 25, wherein the interposer includes a redistribution insulating layer 141 including a photosensitive insulating material. In Species C, wherein a top surface of the upper pad 16 is not in contact with a bottom surface of the lower pad 25, wherein a distance between the interposer and the second semiconductor chip is greater than the height of the first semiconductor chip.
These difference in the package structures among Species A, B and C require different search keywords, strategies and thus impart serious burden.
Therefore, the restriction requirement has been maintained and made FINAL.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 10-12, 13, 15, 18-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin et al. (US 20230187365 A1; hereinafter “Lin”).
In re claim 1, Lin discloses, in figs. 1-2, 3E, 4B, 5E, 6, a semiconductor package comprising:
an interposer 551 (¶142);
a first semiconductor chip 100b on the interposer 551 (¶144);
a connection structure 467 on the interposer 551 (¶144); and
a second semiconductor chip 200b on the first semiconductor chip 100b and the connection structure 467 (figs. 5E, 6; ¶124, 144),
wherein the first semiconductor chip 100b includes a first substrate 2 (¶91),
a first interconnection structure 20 on a top surface of the first substrate 2 (fig. 3E; ¶91), and
a first input/output circuit 4 between the first substrate 2 and the first interconnection structure 20 (¶20, 91, 144),
wherein the second semiconductor chip 200b includes a second interconnection structure 20 (fig. 5E; ¶91),
a second substrate 2 on a top surface of the second interconnection structure 20, and a second input/output circuit 4 between the second substrate 2 and the second interconnection structure 20,
wherein the connection structure 467 include a connection substrate 2, and a connection through-via 157 penetrating the connection substrate 2 and electrically connecting the second semiconductor chip 200b and the interposer 551 (fig. 4B, ¶117), and
wherein the first input/output circuit (e.g., 4 in the bottom semiconductor chip 100b) and the second input/output circuit (e.g., 4 in the top semiconductor chip 200b) are electrically connected to each other.
In re claim 2, Lin discloses in figs. 1-2, 3E, 4B, 5E, 6, the semiconductor package of claim 1,
wherein the first semiconductor chip 100b further includes an upper pad 6a electrically connected to the first input/output circuit 4,
wherein the second semiconductor chip 200b further includes a lower pad 6a electrically connected to the second input/output circuit 4 (fig. 5E; ¶128), and
wherein a top surface of the upper pad 6a of the first semiconductor chip 100b faces a bottom surface of the lower pad 6a of the second semiconductor chip 200b.
In re claim 3, Lin discloses in figs. 1-2, 3E, 4B, 5E, 6, the semiconductor package of claim 2, wherein the top surface of the upper pad 6a of the first semiconductor chip 100b is in contact with the bottom surface of the lower pad 6a of the second semiconductor chip 200b (fig. 6 shows as an amplified inset in the middle of the drawing and described in ¶149).
In re claim 4, Lin discloses in figs. 1-2, 3E, 4B, 5E, 6, the semiconductor package of claim 1, wherein the connection structure 467 further includes an upper connection pad 34 electrically connected to the connection through-via 157 (fig. 4B; ¶117), and wherein the second semiconductor chip 200b further includes a lower pad 6a (¶128) in contact with the upper connection pad 34 of the connection structure 467.
In re claim 5, Lin discloses in figs. 1-2, 3E, 4B, 5E, 6, the semiconductor package of claim 1, wherein the second semiconductor chip 200b overlaps with the first semiconductor chip 100b and the connection structure 467 in a vertical direction.
In re claim 10, Lin discloses, in figs. 1-2, 3E, 4B, 5E, 6, a semiconductor package comprising:
an interposer 551 (¶142);
a first semiconductor chip 100b on the interposer 551 (¶144);
a connection structure 467 on the interposer 551 (¶144); and
a second semiconductor chip 100a on the first semiconductor chip 100b and the connection structure 467 (¶144),
wherein the second semiconductor chip 100a overlaps with the first semiconductor chip 100b and the connection structure 467 in a vertical direction, and
wherein a height of the first semiconductor chip 100b is equal to a height of the connection structure 467 (see fig. 6 annotated by the Examiner, a height of the first semiconductor chip 100b is equal to a height of the connection structure 467 shown as H).
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In re claim 11, Lin discloses in figs. 1-2, 3E, 4B, 5E, 6, the semiconductor package of claim 10,
wherein a top surface of the first semiconductor chip 100b is coplanar with a top surface of the connection structure 467, and
wherein a bottom surface of the first semiconductor chip 100b is coplanar with a bottom surface of the connection structure 467.
In re claim 12, Lin discloses in figs. 1-2, 3E, 4B, 5E, 6, the semiconductor package of claim 10,
wherein the connection structure 467 includes a connection substrate 2 (¶114), and
a connection through-via 157 penetrating the connection substrate 2 (¶114), and
wherein the connection through-via 157 electrically connects the second semiconductor chip 100a to the interposer 551.
In re claim 13, Lin discloses in 1-2, 3E, 4B, 5E, 6, the semiconductor package of claim 12,
wherein the second semiconductor chip 100a includes a substrate 2 (¶91), and a lower pad 6a between the substrate of the second semiconductor chip 2 and the connection substrate of the connection structure 2,
wherein the connection structure 467 further includes an upper connection pad 34 (fig. 4B; ¶117) in contact with the lower pad 6a.
In re claim 15, Lin discloses, in figs. 1-2, 3E, 4B, 5E, 6, the semiconductor package of claim 10,
wherein the first semiconductor chip 100b includes a first input/output circuit (“the bottom semiconductor IC chip 100b of each of its subsystem units 280 may have a first set of small I/O circuits”; ¶149. Hereinafter “I/O-1”),
wherein the second semiconductor chip 100a includes a second input/output circuit (Hereinafter “I/O-2”) electrically connected to the first input/output circuit (“the bottom semiconductor IC chip 100b of each of its subsystem units 280 may have a first set of small I/O circuits coupling respectively to a second set of small I/O circuits of the top semiconductor IC chip 100a of said each of its subsystem units 280 through the bonding of a set of metal pads 6a of the bottom semiconductor IC chip 100b of said each of its subsystem units 280 to a set of metal pads 6a of the top semiconductor IC chip 100a of said each of its subsystem units 280 respectively”; ¶149), and
wherein the first input/output circuit (I/O-1) overlaps with the second input/output circuit (I/O-2) in the vertical direction (¶149).
In re claim 18, Lin discloses, in figs. 1-2, 3E, 4B, 5E, 6, the semiconductor package of claim 10,
wherein the first semiconductor chip 100b and the connection structure 467 are spaced apart from each other in a horizontal direction,
the semiconductor package further comprising:
an insulating layer 92 surrounding the first semiconductor chip 100b and the connection structure 467 (¶146),
wherein a portion of the insulating layer 92 is disposed between the first semiconductor chip 100b and the connection structure 467.
In re claim 19, Lin discloses, in figs. 1-2, 3E, 4B, 5E, 8, a semiconductor package comprising:
an interposer 551 (¶142);
a first semiconductor chip (upper chiplet 200b of the lower chip module 400 in figs. 5E, 8; hereinafter Chip1”) on the interposer 551 (¶124, 154);
a connection structure (lower chiplet 200a of the lower chip module 400 in figs. 5E, 8) on the interposer 551 (¶148);
an insulating layer 564 surrounding the first semiconductor chip Chip1 and the connection structure (i.e., the lower chiplet 200a of the lower chip module 400) (fig. 8; ¶148);
a second semiconductor chip (200b in the upper chip module 400; hereinafter “Chip2”) on the first semiconductor chip Chip1 and the connection structure (figs. 5E, 7; ¶124, 144. Note: upper chip module 400 of fig. 5E is flipped in fig. 8),
third semiconductor chips (200a in in the upper chip module 400, 545, 545) on the second semiconductor chip Chip2 (¶155, 165);
a dummy semiconductor chip 141 on the first semiconductor chip Chip1 (fig. 8; ¶164); and
a molding layer 92 surrounding the dummy semiconductor chip 141, the second semiconductor chip 200b and the third semiconductor chips (i.e., 200a in the upper chip module 400, 545, 545) (¶157),
wherein the first semiconductor chip Chip1 (i.e., 200b) includes a first substrate 2, a first interconnection structure 20 on a top surface of the first substrate 2 (fig. 3E; ¶91), a first input/output circuit 4 between the first substrate 2 and the first interconnection structure 20 (¶20, 91, 144), and an upper pad 6a electrically connected to the first input/output circuit 4 (¶108),
wherein the second semiconductor chip Chip2 includes a second interconnection structure 20, a second substrate 2 on a top surface of the second interconnection structure 20, a second input/output circuit 4 between the second substrate 2 and the second interconnection structure 20, and a lower pad 6a electrically connected to the second input/output circuit 4 (fig. 5E upside down, as shown in the package of fig. 8; ¶124, 137),
wherein the connection structure (i.e., lower chiplet 200a of the lower chip module 400 in figs. 5E, 7) includes a connection substrate 2, and a connection through-via 157 penetrating the connection substrate 2 and electrically connecting the second semiconductor chip Chip2 to the interposer 551 (fig. 7; ¶156), and
wherein a top surface of the upper pad 6a is in contact with a bottom surface of the lower pad 6a.
In re claim 20, Lin discloses, in figs. 1-2, 3E, 4B, 5E, 8, the semiconductor package of claim 19, wherein a length of an electrical path connecting the first input/output circuit 4 to the second input/output circuit 4 is within a range from several µm to several tens µm (see note below).
Note: A length of an electrical path connecting the first input/output circuit 4 to the second input/output circuit 4 is at least the summation of the thicknesses of two first interconnection scheme for a chip (FISC) 20 and the thicknesses of two metal pads 6a. Based on [0093], each FISC 20 comprising 5 insulating dielectric layers 12, wherein each dielectric layers 12 has thickness between 0.1 and 2 micrometers. Therefore, each FISC 20 has thickness between 0. and 10 micrometers. Based on [0108], each metal pad 6a has a thickness of at least 0.004 to 0.55 micrometers. Thus, A length of an electrical path connecting the first input/output circuit 4 to the second input/output circuit 4 is in a range between 1.08 µm to 21.10 µm, which anticipates the claimed range.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin, as applied to claim 1 above, and further in view of Chen et al. (US 20240145431 A1; hereinafter “Chen”).
In re claim 6, Lin discloses in figs. 1-2, 3E, 4B, 5E, 6, the semiconductor package of claim 1, further comprising: wherein the first semiconductor chip 100b further includes an upper protective layer 52 on a top surface of the first interconnection structure 20 (fig. 3E; ¶108).
Lin does not expressly disclose in the embodiment shown in fig. 6, a dummy semiconductor chip on the first semiconductor chip, wherein the dummy semiconductor chip includes a dummy protective layer in contact with a top surface of the upper protective layer of the first semiconductor chip.
In the same field of endeavor, Chen discloses, in figs. 1-15, a semiconductor package comprising:
a dummy semiconductor chip 80B on a first semiconductor chip 50A (¶46-47),
wherein the dummy semiconductor chip 80b includes a dummy protective layer 68 in contact with a top surface of an upper protective layer 82 of the first semiconductor chip 50A (¶48).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Chen into the package of Lin to attain integration density of the stacked and bonded semiconductor devices and further reducing the physical size of a semiconductor device (¶2-3 of Chen).
In re claim 7, Lin, as modified by Chen, discloses the semiconductor package of claim 6, Chen further discloses wherein the first semiconductor chip further comprises:
an upper pad 84 surrounded by the upper protective layer 78 of the first semiconductor chip 50A (¶44),
wherein a top surface of the upper pad of the first semiconductor chip (e.g., pad 84 in fig. 15 of Chen) is in contact with a bottom surface of the dummy protective layer of the dummy semiconductor chip (fig. 15: layer 68 of Chen).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin, as applied to claim 1 above, and further in view of Hsiao et al. (US 20140070422 A1; hereinafter “Hsiao”).
In re claim 9, Lin discloses, in figs. 1-2, 3E, 4B, 5E, 6, the semiconductor package of claim 1, wherein the interposer 551 includes a redistribution pattern 67 and a redistribution insulating layer 112 surrounding the redistribution pattern 67 (fig. 6; ¶142).
Lin does not expressly disclose wherein the redistribution insulating layer 112 includes a photosensitive insulating material.
In the same field of endeavor, Hsiao discloses, in figs. 1-3, a semiconductor package, comprising: wherein a redistribution insulating layer 11 includes a photosensitive insulating material (¶10).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form the redistribution insulating layer of Lin including a photosensitive insulating material as Hsiao discloses photosensitive insulating material can be easily patterned using a lithography mask similar to a photo resist (¶10 of Hsiao).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin, as applied to claim 10 above, and further in view of Gandhi et al. (US 20210366873 A1; hereinafter “Gandhi”).
In re claim 14, Lin discloses in fig. 6, the semiconductor package of claim 10 outlined above.
Lin does not expressly disclose in fig. 6, the semiconductor package further comprising:
third semiconductor chips on the second semiconductor chip; and
a dummy semiconductor chip on the first semiconductor chip,
wherein the third semiconductor chips include an uppermost semiconductor chip, and
wherein a top surface of the uppermost semiconductor chip is coplanar with a top surface of the dummy semiconductor chip.
In the same field of endeavor, Gandhi discloses in fig. 6, a semiconductor package, comprising:
third semiconductor chips 106, 106 on a second semiconductor chip 104 (¶24); and
a dummy semiconductor chip 602 (¶58) on a first semiconductor chip 460 (¶49),
wherein the third semiconductor chips 106, 106 include an uppermost semiconductor chip 106, and
wherein a top surface of the uppermost semiconductor chip 106 is coplanar with a top surface of the dummy semiconductor chip 602.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Gandhi into the package of Lin in order to enable chip package assemblies having improved modularity that enables shorter design and build lead times at reasonable costs as compared to conventional monolithic solutions (¶2-4 of Gandhi).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin, as applied to claim 10 above.
In re claim 16, Lin discloses in fig. 1-2, 3E, 4B, 5E, 6, the semiconductor package of claim 10,
wherein the first semiconductor chip 100b includes an overlapping portion overlapping with the second semiconductor chip 100a in the vertical direction.
Lin does not expressly disclose in the embodiment shown in fig. 6, wherein a width of the first semiconductor chip is equal to or greater than twice a width of the overlapping portion.
However, Lin discloses in the embodiment shown in fig. 27B, wherein a width of a bottom first semiconductor chip 100 is greater than an overlapping portion with an upper semiconductor chip 100 (¶351-352).
Lin does not expressly disclose a width of the first semiconductor chip is equal to or greater than twice a width of the overlapping portion.
However, it has been held to be within the general skill of a worker in the art to select widths of a lower semiconductor chip and an upper semiconductor chip and the overlapping areas of the two chips in a stacked multi-chip package on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. A person of ordinary skills in the art is motivated to select the width of the first semiconductor chip is equal to or greater than twice a width of the overlapping portion in order to accommodate higher number of chips in the upper layer and increase device density in the package.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen et al. (US 20230014913 A1) teaches stacked chips with upper chip on a lower chip and a connection structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893
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