DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 6-8 and 15-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bakir et al. US 2010/0187683 A1.
Regarding claims 1, 2 and 6-8, Bakir discloses:
An electrical device (Figs. 16 and 17) comprising:
a first die level (top portion of 1700) including first thermal cooling through silicon vias (TSV) (1630) and fluidic channels (1615); and
a second die level (bottom portion of 1700) including second thermal cooling through silicon vias (TSV) (1630) and electrical connection through silicon vias (TSV) (1625), wherein at least one active device layer (Si die portion) is in a level of the electrical device that is separate from a level containing the first thermal cooling through silicon vias (TSV), the second thermal cooling through silicon vias and the electrical connection through silicon vias (TSV) (SI Die separate from 1630s and 1625s).
(claim 2) Fig. 17.
(claim 6) Figs. 16, 17; stack shown separated by 1615s.
(claim 7) Figs. 16, 17; 1625s electrical connection and 1630s cooling.
(claim 8) Fig. 16; Si Die.
Regarding claims 15-17, Bakir discloses:
An electrical device (Figs. 16 and 17) comprising:
thermal cooling through silicon vias (TSV) (1630) embedded through a silicon-containing layer (1700), wherein the silicon-containing layer is at one end of a stacked structure providing the electrical device (Si Die); and
at least one active device layer in the stacked structure that is present a level of the electrical device that is separate from a level containing the thermal cooling through silicon vias (TSV) (Si Die separated from the overlying 1630s).
(claim 16) Figs 16, 17; 1630 bottom surface coplanar with Si Die surface.
(claim 17) Figs 16, 17; 1630 top surface protrudes beyond Si Die surface.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bakir et al. US 2010/0187683 A1.
Regarding claims 3 and 4, although Bakir does not specifically disclose “(claim 3) wherein the first die level includes metal wiring in a first back end of the line (BEOL) level that is in contact with the first thermal cooling through silicon vias (TSV) that are embedded in the first silicon containing layer; and (claim 4) wherein the first back end of the line (BEOL) level is positioned between a first active device layer of the at least one active device layer and the first silicon containing layer having the first thermal cooling through silicon vias (TSV) present therein”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to understand that BEOL features are employed in semiconductors to electrically integrated/interconnect the active transistors on the bottommost layer to the other internal wirings and external connections. As a result, such features would be readily understood as being above the active regions of the Si Die with the cooling through silicon vias arranged and connected above.
Allowable Subject Matter
Claims 5, 9, 10 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art fails to teach or clearly suggest the limitations of claim 5 stating “wherein the first active device layer is present on a first back side interconnect”; of claim 9 stating “wherein the second active device layer is separated from the second silicon containing layer by a second back end of the line (BEOL) level, the second thermal cooling through silicon vias (TSV) and the electrical connection through silicon vias (TSV) extending into the second back end of the line (BEOL) level”; of claim 10 stating “wherein the second active device layer is present on a second back side interconnect”; of claim 18 stating “further comprising a back end of the line (BEOL) level that is in contact with the thermal cooling through silicon vias (TSV) that are embedded in the silicon containing layer, wherein the back end of the line (BEOL) level is positioned between the at least one active device layer and the silicon-containing layer having the thermal cooling through silicon vias (TSV) present therein”; and of claim 20 stating “wherein the stacked structure does not include well isolation for fluidic channels”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention.
Claims 11-14 are allowed.
The following is an examiner’s statement of reasons for allowance:
The prior art fails to teach or clearly suggest the limitations of claim 11 stating “wherein a cap layer for the fluidic channel level includes an opening therethrough to channels containing the thermal cooling through silicon vias (TSV)”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERROL V FERNANDES/Primary Examiner, AU 2893