DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species D, represented by figure 12 and claims 1-20 in the reply filed on March 31, 2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 15, 2023 was considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koo et al. (US 2022/0336497 A1) (“Koo”), in view of Lee et al. (US 2021/0193661 A1) (“Lee”).
Regarding claim 1, Koo teaches at least in figures 3-4:
a source line (105) extending in a first horizontal direction (X) on a substrate (101);
a channel layer (240) extending in a vertical direction (Z) perpendicular to an upper surface of the substrate (101), and
(a channel layer) comprising (detailed below)
a first end (bottom of 240),
a second end (top of 240) opposite to the first end (bottom of 240), and
a channel layer sidewall (sidewall of 240) extending from the first end (bottom of 240) to the second end (top of 240),
the first end (bottom of 240) being disposed on the source line (105);
a trap layer (220) disposed on the channel layer sidewall (sidewall of 240);
a gate insulating layer (210) disposed on an outer surface of the trap layer (220);
a word line (120a-c) disposed on at least one sidewall of the gate insulating layer (210) and extending in a second horizontal direction crossing the first horizontal direction (this is shown in figure 2);
a drain area (260) disposed on the second end of the channel layer (240) and comprising a material having a work function equal to or smaller than 4.2 eV (¶ 0052, where 260 can be formed of some of the same materials as disclosed in Applicant’s ¶ 0045); and
a bit line (not shown) disposed on the drain area (¶ 0051 where a bit line may be connected to 260).
Koo does not show:
The bit line extends in the first horizontal direction.
Lee teaches at least in figure 3:
The bit line (154) extends in the first horizontal direction (second direction; in figure 3 one can see the source line 102 and the bit line 154 both extend in the same direction).
It would have been obvious to one of ordinary skill in the art to combine the aforementioned references as Koo does not teach how the bit lines are connected. Thus, it would have been obvious to one of ordinary skill in the art to combine said references.
Regarding claim 2, Koo teaches at least in figures 3-4:
wherein the drain area includes a material having a work function equal to or smaller than 4.2 eV comprises at least one metal or metal nitride (¶ 0052).
Regarding claim 3, Koo teaches at least in figures 3-4:
wherein the drain area includes at least one of titanium nitride (TiN), aluminum (Al), thallium (Tl), indium (In), cadmium (Cd), hafnium (Hf), manganese (Mn), tantalum (Ta), or zirconium (Zr) (¶ 0052).
Regarding claim 4, Lee teaches at least in figure 3:
wherein the drain area (Lee 150 is equivalent to Koo 260) is disposed between the channel layer (lee 138) and the bit line (152).
Regarding claim 5, Koo teaches at least in figures 3-4:
wherein the channel layer has a cylindrical shape extending in the vertical direction, and the word line surrounds the channel layer when viewed in plan view (this is shown in figure 3).
Regarding claim 6, Koo teaches at least in figures 3-4:
wherein the channel layer (240) includes (detailed below)
a bottom portion at the first end that is disposed on an upper surface of the source line (240 has a bottom portion on 105), and
a vertical extension portion extending from the bottom portion towards the second end in the vertical direction (240 has such a vertical portion extending), and
the trap layer covers an outer sidewall of the vertical extension portion (220 so covers).
Regarding claim 9, Koo teaches at least in figures 3-4:
wherein the source line comprises p-type dopant-doped polysilicon (¶ 0039
Regarding claim 10, Koo teaches at least in figures 3-4:
wherein the source line includes at least one of titanium nitride (TiN), aluminum (Al), thallium (Tl), indium (In), cadmium (Cd), hafnium (Hf), manganese (Mn), tantalum (Ta), zirconium (Zr), or tungsten (W) (¶ 0039).
Regarding claim 11, Koo teaches at least in figures 3-4:
wherein the semiconductor device is a capacitor-less dynamic random access memory (DRAM) device (This is considered a relabeling of the device. Because the prior art device has the same claimed features it can likewise be relabeled. Alternatively, or additionally, a nand device can be a DRAM device. As a DRAM device is how the device is used. See MPEP 2173.05(q). This use of the device of claim 1 as a DRAM does not add patentable weight).
Allowable Subject Matter
Claims 7-8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7, Koo teaches at least in figures 3-4:
a buried pillar (250) disposed on an inner sidewall of the vertical extension portion (sidewalls of 240),
wherein the drain area (260) is disposed on an upper surface of the buried pillar (250)
The prior art does not teach:
The drain area is disposed on an upper surface of the vertical extension portion.
Examiner understands upper surface of the vertical extension portion to mean that Applicant’s 142 is directly on top and contacting Applicant’s 136(VP).
Claims 12-20 are allowed.
The following is an examiner’s statement of reasons for allowance: see below.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Regarding claim 12,
Claim 12 requires “a drain area disposed at a vertical level higher than the word line, contacting an upper surface of the channel layer”. This limitation renders the claim allowable for the same reason as claim 7 above.
Regarding claim 19,
Claim 19 requires “a drain area disposed on an upper surface of the channel layer”. This limitation renders the claim allowable for the same reason as claim 7 above.
Conclusion
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/VINCENT WALL/Primary Examiner, Art Unit 2898
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