DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on January 3, 2024 was considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
At least claim 1 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over at least claim 1 of copending Application No. 18/312,827 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other for the reasons given below.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Current Application
Reference Application
A capacitor comprising:
a first thin film electrode layer;
a second thin film electrode layer;
a dielectric layer between the first thin film electrode layer and the second thin film electrode layer; and
an interlayer between the second thin film electrode layer and the dielectric layer,
the interlayer including a first metal oxide and a second metal oxide having a rutile phase,
wherein the dielectric layer includes a third metal oxide having a rutile phase,
the first metal oxide includes at least one of Al2O3 or MgO,
the second metal oxide includes at least one of SnO2, GeO2, or MnO2,
the third metal oxide includes at least one of TiO2, Ti1-xGaxO2 (0.01≤x≤0.1), Ti1-xAlxO2 (0.01≤x≤0.1), Ti1-xLaxO2 (0.01≤x≤0.1), Ti1-xBxO2 (0.01≤x≤0.1), Ti1-xInxO2 (0.01≤x≤0.1), Ti1-xScxO2 (0.01≤x≤0.1), or Ti1-xYxO2 (0.01≤x≤0.1), and
the first metal oxide, the second metal oxide, and the third metal oxide have different compositions from each other.
A capacitor comprising:
a first thin-film electrode layer;
a second thin-film electrode layer;
a dielectric layer between the first thin-film electrode layer and the second thin-film electrode layer; and
a first interlayer being at least one of between the first thin-film electrode layer and the dielectric layer and between the second thin-film electrode layer and the dielectric layer,
the first interlayer including first metal oxide, wherein at least one of the first thin-film electrode layer and the second thin- film electrode layer includes second metal oxide having a rutile crystal structure and including non-noble metal,
the dielectric layer includes third metal oxide having a dielectric rutile crystal structure,
the first metal oxide includes GeO2, and the third metal oxide includes TiO2, and a thickness of the first interlayer is smaller than that of the dielectric layer.
the first metal oxide, the second metal oxide, and the third metal oxide have different compositions from one another,
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7-8, 10-13, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moon et al. (US 2020/0091279 A1) (“Moon”), in view of Liu et al., "First-principles study of structural, elastic, electronic and optical properties of rutile GeO2 and a-quartz GeO2", Solid State Sciences 12 (2010) 1748e1755 (“Liu”).
Regarding claim 1, Moon teaches at least in figure 1:
a first thin film electrode layer (130);
a second thin film electrode layer (140);
a dielectric layer (150) between the first thin film electrode layer (130) and the second thin film electrode layer (140); and
an interlayer (160-170) between the second thin film electrode layer (140) and the dielectric layer (150),
the interlayer (160-170) including a first metal oxide (170) and a second metal oxide (160),
wherein the dielectric layer (150) includes a third metal oxide having a rutile phase (¶ 0030),
the first metal oxide (170) includes at least one of Al2O3 or MgO (¶ 0038),
the second metal oxide (160) includes at least one of SnO2, GeO2, or MnO2 (¶ 0031),
the third metal oxide includes at least one of TiO2, Ti1-xGaxO2 (0.01≤x≤0.1), Ti1-xAlxO2 (0.01≤x≤0.1), Ti1-xLaxO2 (0.01≤x≤0.1), Ti1-xBxO2 (0.01≤x≤0.1), Ti1-xInxO2 (0.01≤x≤0.1), Ti1-xScxO2 (0.01≤x≤0.1), or Ti1-xYxO2 (0.01≤x≤0.1) (¶ 0030), and
the first metal oxide (170),
the second metal oxide (160), and
the third metal oxide (150) have different compositions from each other (each of the above layers have a different composition as they are different materials).
Moon does not teach:
a second metal oxide having a rutile phase.
Liu teaches:
There are three stable forms of GeO2: rutile, alpha-quartz, and amorphous glass. Pg. 1748, col. 1 at ¶ 1.
One of ordinary skill in the art seeing GeO2 in Moon would have known about these three stable forms of GeO2. It would have been obvious to one of ordinary skill in the art to try rutile GeO2 as there are a limited amount of options and based upon Liu, and it would have been obvious for one of ordinary skill in the art to try rutile GeO2 based upon their design requirements for the material when compared to the other stable forms of GeO2.
Regarding claim 2, Moon teaches at least in figure 1:
wherein a ratio of a content of the second metal oxide to a content of the first metal oxide is at least about 10 at% and not more than about 90 at% (this is obvious based upon the thickness of each of the layers of the second metal oxide (160) and the first metal oxide (170) (see ¶¶ 0032 and 40).
Regarding claim 3, Moon teaches at least in figure 1:
wherein the interlayer (160-170) includes a first interlayer (170) and a second interlayer (160),
the second interlayer (160) between the first interlayer (170) and the dielectric layer (150),
the first interlayer (170) includes the first metal oxide (see claim 1), and
the second interlayer (160) includes the second metal oxide (see claim 1).
Regarding claim 4, Moon does not teach:
wherein a thickness of the second interlayer is less than 1 Å.
However, this is considered a change in size or proportion of the second interlayer. There is no evidence that the device with the claimed thickness would perform differently than the prior art device having said thickness. MPEP 2144.04(IV)(A).
Regarding claim 7, Moon teaches at least in figure 1:
wherein a chemical potential of the second metal oxide is greater than a chemical potential of the third metal oxide (This is obvious as the prior art teaches the same materials as Applicant, and therefore it would obviously have this same claimed characteristic. MPEP 2112).
Regarding claim 8, Moon teaches at least in figure 1:
Claim 8 contains all of the limitations of claim 1 and 7 except for.
A band gap energy of the first metal oxide is 5.0 eV or more.
However, the band gap energy of a device is considered a characteristic of said device. Because the prior art teaches the same materials disclosed by Applicant it would have been obvious that it would have the same characteristic.
Regarding claim 10,
Claim 10 contains the subject matter of claim 2 and is rejected for the same reasons.
Regarding claim 11,
Claim 11 contains the subject matter of claim 3 and is rejected for the same reasons.
Regarding claim 12,
Claim 12 contains the subject matter of claim 4 and is rejected for the same reasons.
Regarding claim 13,
Claim 11 contains the subject matter of claim 1 and is rejected for the same reasons.
Regarding claim 17, Moon teaches at least in figure 1:
a transistor; and the capacitor of claim 1 electrically connected to the transistor (¶ 0025).
Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moon, in view of Liu, in view of Shiratake (US 2007/0082440 A1) (“Shiratake”).
Regarding claim 18, Shiratake teaches at least in figure 20:
wherein the transistor comprises (detailed below):
a semiconductor substrate (100) including
a source region (116 on left or right),
a drain region (116 in the middle), and
a channel region (the channel surrounds 108) between the source region (116 on left or right) and the drain region (116 in the middle); and
a gate stack (109-110) on the semiconductor substrate (100) and facing the channel region (109-110 so face the channel),
the gate stack (109-110) including a gate insulating layer (109) and a gate electrode (110).
It would have been obvious to one of ordinary skill in the art to combine Shiratake with Moon and Liu as Moon does not teach what the transistor looks like. Therefore, it would have been obvious to one of ordinary skill in the art to search for other references which teach the transistor structure.
Regarding claim 19, Shiratake teaches at least in figure 20:
wherein the transistor comprises (detailed below):
semiconductor substrate (100) including
a source region (116 on left or right),
a drain region (116 in the middle), and
a channel region (the channel surrounds 108) between the source region (116 on left or right) and the drain region (116 in the middle); and
and a gate stack (109-110) in a trench (108) extending into a surface of the semiconductor substrate (100),
the gate stack (109-110) facing the channel region (the channel surrounds 108) and including a gate insulating layer (109) and a gate electrode (110).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moon, in view of Liu, in view of Myung et al. (US 2014/0061745 A1) (“Myung”).
Regarding claim 20, Moon teaches:
wherein the capacitor and the transistor are included in a memory unit (the capacitor and transistor of Moon can be called a memory unit); and
Moon does not teach:
the electronic device further comprises (detailed below)
a control unit electrically connected to the memory unit, the control unit configured to the memory unit.
Myung teaches at least in figures 7-8:
the electronic device further comprises (detailed below)
a control unit (1020) electrically connected to the memory unit (1010),
the control unit (1020) configured to the memory unit (1010).
It would have been obvious to one of ordinary skill in the art to add the control unit to the device of Moon as this would allow one to use an array of memory units (memory chip).
Potentially Allowable Subject Matter
If Applicant is able to remove the double patenting rejection, claims 5-6, 9, and 14-16 would be objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5, Moon does not teach:
a third interlayer between the first thin film electrode layer and the dielectric layer, the third interlayer including a fourth metal oxide having a rutile-phase crystal structure,
wherein the fourth metal oxide includes at least one of SnO2, GeO2, or MnO2.
Regarding claim 6, Moon teaches at least in figure 1:
wherein the first thin film electrode layer comprises (detailed below):
a second lower electrode layer (130) spaced apart from the dielectric layer (150), and
a first lower electrode layer (132) between the second lower electrode layer (130) and the dielectric layer (150),
Moon does not teach:
the first lower electrode layer including a fifth metal oxide having a rutile phase, and wherein the fifth metal oxide includes at least one of MoO2, VO2, Mo1-xNbxO2 (0.01≤x≤0.1), Mo1-xTaxO2 (0.01≤x≤0.1), Mo1-xSbxO2 (0.01≤x≤0.1), Mo1-xMnxO2 (0.01≤x≤0.1), Mo1-xFexO2 (0.01≤x≤0.1), V1-xNbxO2 (0.01≤x≤0.1), V1-xTaxO2 (0.01≤x≤0.1), V1-xSbxO2 (0.01≤x≤0.1), V1-xMnxO2 (0.01≤x≤0.1), or V1-xFexO2 (0.01≤x≤0.1).
This is because Moon teaches the first lower electrode layer (132) is formed of Ti.
Regarding claim 9,
Claim 9 is allowable for the same reasons as claim 5 above.
Regarding claim 14,
Claim 14 is allowable for the same reasons as claim 5 above.
Conclusion
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/VINCENT WALL/ Primary Examiner, Art Unit 2898