DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 11 objected to because of the following informalities: Claim 11 recites “channel layers layers…”. The word “layers” is repeated. Appropriate correction is required. The second “layers” should be removed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Yi(US20200395446A1) in view of Cheng(US10374059B2).
With respect to Claim 1, Yi teaches in Fig 2, a semiconductor device comprising:
a plurality of gate structures (Fig 2; 130; ¶ [0018]) stacked with a plurality of core channel layers (Fig 2; 120; ¶ [0019]) comprising a first semiconductor material (120; ¶ [0023]);
a source/drain (Fig 2; 107(b); ¶ [0038]) region disposed on a side of the plurality of gate structures (Fig 2; 130; ¶ [0018]) and the plurality of core channel layers (Fig 2; 120; ¶ [0019]); and
a plurality of buffer semiconductor layers (Fig 2; 107(a); ¶ [0038]), wherein respective ones of the plurality of buffer semiconductor layers are disposed between respective ones of the plurality of core channel layers (Fig 2; 120; ¶ [0019]) and the source/drain region (Fig 2; 107(b); ¶ [0038]).
Yi does not teach a plurality of cladding channel layers disposed around the plurality of gate structures and comprising a second semiconductor material different from the first semiconductor material;
Cheng teaches in Fig 2K-1, a plurality of cladding channel layers (Fig 2K-1; 154, 156, 160, 162; Column 17 Line 45-51 and Column 18 Line 57-60) disposed around the plurality of gate structures (Fig 2K-1; 164; Column 21 Line 6-10) and comprising a second semiconductor material (Fig 2K-1; 154; Column 16 Line 10-14) different from the first semiconductor material;
It would be obvious to one with ordinary skill in the art before the effective filling date of the invention to combine the invention of Yi, a semiconductor device with stacked gate structures and channel core structures in contact with a drain region and buffer layer and the invention of Cheng, a semiconductor device with stacked gate structures, channel structures and a plurality of layers (cladding layers) surrounding the gate structures. This combination would produce a semiconductor device with stacked gate structures surrounded by a plurality of layers, stacked channel structures in contact with the buffer layer and the drain region. The plurality of layers surrounding the gate structures includes a layer to protect Cheng(154; Column 16 Line 10-14) the gate structure to enhance performance.
With respect to Claim 2, Yi teaches the semiconductor device of claim 1, wherein the first semiconductor material comprises silicon (120; ¶ [0023]).
Yi does not teach the second semiconductor material comprises silicon germanium.
Cheng teaches the second semiconductor material comprises silicon germanium (Fig 2K-1; 154; Column 16 Line 10-14).
It would be obvious to one with ordinary skill in the art before the effective filling date of the invention to combine the invention of Yi, a semiconductor device with stacked gate structures and channel core structures being made of silicon, and the invention of Cheng a semiconductor device with stacked gate structures, channel core structures and a plurality of layers comprising of silicon germanium surrounding the gate structures. This combination would produce a semiconductor device with stacked gate structures surrounded by a plurality of layers comprising of silicon germanium. The plurality of layers surrounding the gate structures make a cladding region that includes silicon germanium, used for protection Cheng(154; Column 16 Line 10-14), while being in contact with the silicon channel layer Cheng(Column 21 Line 23-26).
With respect to Claim 3, Yi and Cheng teach the semiconductor device of claim 2.
Yi teaches in ¶ [0069] wherein the source/drain region corresponds to a p-type transistor (107; ¶ [0069]) and comprises doped silicon germanium (107; ¶ [0069]).
With respect to Claim 4, Yi and Cheng teach the semiconductor device of claim 1.
Yi teaches wherein at least one layer surrounds a gate structure of the plurality of layers surrounds a gate structure of the plurality of gate structures (Fig 2; 110 and 130; ¶ [0024]).
Yi does not teach the plurality of cladding channel.
Cheng teaches plurality of cladding channel layers (Fig 2K-1; 154, 156, 160, 162; Column 17 Line 45-51 and Column 18 Line 57-60).
It would be obvious to one with ordinary skill in the art before the effective filling date of the invention to combine the invention of Yi, a semiconductor device with stacked gate structures and channel core structures and the invention of Cheng a semiconductor device with stacked gate structures, channel core structures and a plurality of layers comprising semiconductor material surrounding the gate structures. This combination would produce a semiconductor device with stacked gate structures surrounded by a plurality of layers. The plurality of layers surrounding the gate structures make a cladding region that includes a protective layer Cheng(154; Column 16 Line 10-14) and an insulating layer Cheng(156; Column 21 Line 10-16) to enhance performance.
With respect to Claim 5, Yi and Cheng teach the semiconductor device of claim 1.
Ti teaches wherein a layer contacts the source/drain region (Fig 3; 110(112 and 111) and 107(b); ¶ [0042]).
Yi does not teach the plurality of cladding channel layers.
Cheng teaches plurality of cladding layer (Fig 2K-1; 154, 156, 160, 162; Column 17 Line 45-51 and Column 18 Line 57-60)
It would be obvious to one with ordinary skill in the art before the effective filling date of the invention to combine the invention of Yi, a semiconductor device with stacked gate structures and a layer that contact the source/drain region, and the invention of Cheng, a semiconductor device with stacked gate structures, surrounded by a plurality of layers comprised of semiconductor material forming a cladding region. This combination would produce a semiconductor device with the cladding region in contact with the source/drain region. The plurality of layers surrounding the gate structures make a cladding region that includes a protective layer Cheng(154; Column 16 Line 10-14) and an insulating layer Cheng(156; Column 21 Line 10-16) to enhance performance. The cladding region being in contact with the source/drain region enhances the control of the current flow in the system with the protective layer and the insulation layer present.
With respect to Claim 6, Yi and Cheng teach the semiconductor device of claim 1.
Yi teaches in Fig 2, wherein the respective ones of the plurality of buffer semiconductor layers contact the source/drain region (Fig 2; 107(a) and 107(b); ¶ [0038]).
With respect to Claim 7, Yi and Cheng teach the semiconductor device of claim 6.
Ti teaches wherein the respective ones of the plurality of buffer semiconductor layers contact the respective ones of the plurality of core channel layers (Fig 2; 107a and 120; ¶ [0038]).
With respect to Claim 8, Yi and Cheng teach the semiconductor device of claim 7.
Yi teaches wherein an area of a first portion of a buffer semiconductor layer of the plurality of buffer semiconductor layers contacting a core channel layer is smaller than an area of a second portion of the buffer semiconductor layer contacting the source/drain region (Fig 2; buffer (107a) contact with channel (120) was smaller thana contact with source/drain(107(b)).
With respect to Claim 9, Yi and Cheng teach the semiconductor device of claim 1.
Yi teaches wherein the plurality of buffer semiconductor layers comprise the first semiconductor material (Fig 2; 107(b); ¶ [0038] SiGe alloy comprises silicon).
With respect to Claim 10, Ti and Cheng teach the semiconductor device of claim 1.
Yi teaches in Fig 2, wherein an area of a first portion of at least one buffer semiconductor layer of the plurality of buffer semiconductor layers on a core channel layer of the plurality of core channel layers is smaller than an area of a second portion of the at least one buffer semiconductor layer on the source/drain region (Fig 2; buffer (107a) contact with channel (120) was smaller thana contact with source/drain(107(b)).
With respect to Claim 11, Yi and Cheng teaches the semiconductor device of claim 1.
Yi teaches wherein respective layers of the plurality of layers are disposed on opposite surfaces of a core channel layer of the plurality of core channel layers (Fig 2; 110 and 120; ¶ [0040]).
Yi does not teach Cladding channel layers and the plurality of cladding channel layers.
Cheng teaches cladding channel layers and the plurality of cladding layer (Fig 2K-1; 154, 156, 160, 162; Column 17 Line 45-51 and Column 18 Line 57-60)
It would be obvious to one with ordinary skill in the art before the effective filling date of the invention to combine the invention of Yi, a semiconductor device with stacked gate structures and channel structures with a layer surrounding the gate structures and deposited on the opposite surfaces of a core channel layer, and the invention of Cheng, a semiconductor device with stacked gate structures, surrounded by a plurality of layer (cladding region). This combination would produce a semiconductor device with stacked gate structures and channel structures with a plurality of layers (cladding region) surrounding the gate structures and deposited on opposite surfaces of a core channel layer. The cladding region that includes a protective layer Cheng(154; Column 16 Line 10-14) and an insulating layer Cheng(156; Column 21 Line 10-16) being deposited on opposite surfaces of the core channel layer providing protection and insulation for the core channel layer as well as the gate structure.
With respect to Claim 12, Yi and Cheng teach the semiconductor device of claim 1.
Yi teaches wherein the layer is disposed directly on the source/drain region (Fig 3 (Region A of Fig 2); 110(112 and 111) and 107b; ¶ [0042]).
Yi does not teach the plurality of cladding channel layers.
Cheng teaches plurality of cladding layer (Fig 2K-1; 154, 156, 160, 162; Column 17 Line 45-51 and Column 18 Line 57-60).
It would be obvious to one with ordinary skill in the art before the effective filling date of the invention to combine the invention of Yi, a semiconductor device with stacked gate structures and channel structures with a layer surrounding the gate structures and deposited on the source/drain region and the invention of Cheng a semiconductor device with stacked gate structures, surrounded by a plurality of layer (cladding region). This combination would produce a semiconductor device with stacked gate structures and channel structures with a plurality of layers (cladding region) surrounding the gate structures and deposited on the source/drain region. The cladding region that includes a protective layer Cheng(154; Column 16 Line 10-14) and an insulating layer Cheng(156; Column 21 Line 10-16) being deposited on the source/drain region provides protection and insulation for the source/drain region as well as the gate structure.
Claim 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng(US10374059B2) in view of Yi(US20200395446A1).
With respect to Claim 13, Cheng teaches in Fig 2J-1, a semiconductor device comprising:
a plurality of core channel layers (Fig 2J-1; 146; Column 12 Line 7-9) alternately stacked with a plurality of cladding channel layers (Fig 2J-1; 154, 160, 162; Column 20 Line 9-15 and Column 18 Line 57-60), wherein the plurality of core channel layers comprise a first semiconductor material (146; Column 11 Line 36-39) and the plurality of cladding channel layers comprise a second semiconductor material (154; Column 16 Line 10-14) different from the first semiconductor material;
a source/drain region (Fig 2J-1; 134; Column 7 Line 65-Column 8 Line 3) disposed on a side of the plurality of core channel layers (Fig 2J-1; 146; Column 12 Line 7-9) and the plurality of cladding channel layers (Fig 2J-1; 154, 160, 162; Column 20 Line 9-15 and Column 18 Line 57-60); and
a plurality of buffer semiconductor layers (Fig 2J-1; 110; Column 3 Line 60-64),
Cheng does not teach wherein respective ones of the plurality of buffer semiconductor layers are disposed between respective ones of the plurality of core channel and the source/drain region.
Yi teaches in Fig 2, wherein respective ones of the plurality of buffer semiconductor layers (Fig 2; 107(a); ¶ [0038]) are disposed between respective ones of the plurality of core channel layers (Fig 2; 120; ¶ [0019]) and the source/drain region (Fig 2; 107(b); ¶ [0038]).
It would be obvious to one with ordinary skill in the art before the effective filling date of the invention to combine the invention of Cheng, a semiconductor device with stacked gate structures, channel structures and a source/drain region and of Yi, a semiconductor device with stacked gate structures and channel core structures with a plurality of buffer semiconductor layers disposed between the core channel layers and the source/drain region. This combination would produce a semiconductor device with stacked gate structures and channel structures with a plurality of buffer semiconductor layers disposed between the core channel layers and the source/drain region. The germanium (Ge) content of the buffer layer gradually increase as it reaches contact with the source/drain region Yi(¶ [0038]) allowing for the electron mobility to gradually change from the core channel to the first and second source/drain regions, controlling the electron flow in the system.
With respect to Claim 14, Cheng and Yi teach the semiconductor device of claim 13.
Cheng teaches in Fig 2J-1 wherein the first semiconductor material comprises silicon (Fig 2J-1; 146; Column 11 Line 36-39) and the second semiconductor material comprises silicon germanium (Fig 2J-1; 154; Column 18 Line 10-14).
With respect to Claim 15, Cheng and Yi teach the semiconductor device of claim 14
Cheng teaches in Fig 2J-1 wherein the source/drain region corresponds to a p-type transistor and comprises doped silicon germanium (Fig 2J-1; 134; Column7 Line 65-Column 8 Line 3) and Column 8 Line 14-21).
With respect to Claim 16, Cheng and Yi teach the semiconductor device of claim 13.
Cheng teaches in Fig 2J-1, wherein respective ones of the plurality of cladding channel layers (Fig 2J-1; 154, 160, 162; Column 20 Line 9-15 and Column 18 Line 57-60) are disposed around respective gate structures of a plurality of gate structures (Fig 2J-1; 164; Column 20 Line 9-12).
With respect to Claim 17, Cheng and Yi teach the semiconductor device of claim 13.
Cheng teach in Fig 2J-1 wherein the respective ones of the plurality of buffer semiconductor layers contact (Fig 2J-1; 110; Column 3 Line 60-64) the source/drain region (Fig 2J-1; 134; Column 7 Line 65-Column 8 Line 3) and the respective ones of the plurality of core channel layers (Fig 2J-1; 110, 134 and 146; Column 4 Line 3-7).
With respect to Claim 18, Cheng teaches in Fig 2J-1 displays a semiconductor device comprising:
a plurality of core channel layers (Fig 2J-1; 146; Column 12 Line 7-9) alternately stacked with a plurality of cladding channel layers (Fig 2J-1; 154, 160, 162; Column 16 Line 10-14 and Column 18 Line 57-60), wherein the plurality of core channel layers comprise a first semiconductor material (Fig 2J-1; 146; Column 11 Line 36-39) and the plurality of cladding channel layers comprise a second semiconductor material (Fig 2J-1; 154; Column 16 Line 10-14) different from the first semiconductor material;
a first source/drain region disposed on a first side of the plurality of core channel layers and the plurality of cladding channel layers (Fig 2J-1; 134 and 132B-left side; Column 7 Line 65-Column 8 Line 3), and a second source/drain region disposed on a second side of the plurality of core channel layers and the plurality of cladding channel layers (Fig 2J-1; 134 and 132B-right side; Column 7 Line 65-Column 8 Line 3); and
a plurality of buffer semiconductor layers (Fig 2J-1; 110; Column 3 Line 60-64).
Cheng does not teach wherein respective ones of the plurality of buffer semiconductor layers are disposed between respective ones of the plurality of core channel layers and one of the first source/drain region and the second source/drain region
Yi teaches in Fig 2, wherein respective ones of the plurality of buffer semiconductor layers (Fig 2; 107(a); ¶ [0038]) are disposed between respective ones of the plurality of core channel layers (Fig 2; 120; ¶ [0019]) and the source/drain region (Fig 2; 107(b); ¶ [0038]).
It would be obvious to one with ordinary skill in the art before the effective filling date of the invention to combine the invention of Cheng, a semiconductor device with stacked gate structures, channel core structures and a first and second source/drain region and of Yi, a semiconductor device with stacked gate structures and channel core structures with a plurality of buffer semiconductor layers disposed between the core channel layers and the first and second source/drain region. This combination would produce a semiconductor device with stacked gate structures and channel structures with a plurality of buffer semiconductor layers disposed between the core channel layers and the first and second source/drain region. The germanium (Ge) content gradually increase as it reaches contact with the source/drain Yi(¶ [0038]) allowing for the electron mobility to gradually change from the core channel layer to the first and second source/drain regions, controlling the electron flow in the system.
With respect to Claim 19, Cheng and Yi teach the semiconductor device of claim 18.
Cheng teaches in Fig 2J-1, wherein the first semiconductor material comprises silicon (Fig 2J-1; 146; Column 11 Line 36-39) and the second semiconductor material comprises silicon germanium (Fig 2J-1; 154, 160, 164; Column 16 Line 10-14 Column 18 Line 57-60).
With respect to Claim 20, Cheng and Yi teach the semiconductor device of claim 19.
Cheng teaches in Fig 2J-1 wherein the plurality of buffer semiconductor layers comprise the first semiconductor material (Fig 2J-1; 110; Column 3 Line 60-64).
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant’s disclosure:
Chuang(US20130154021A1); A method to fabricate a stacked semiconductor device comprising a gate electrode and capping layers.
Li(US20070111448A1); A semiconductor device comprising transistors
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/B.Q.R./Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817