DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
2. Applicant's election with traverse of Species I in the reply filed on June 22, 2026 is acknowledged. The traversal is on the grounds that examination of Species II would not impose a search burden. This is not found persuasive because prior art disclosing Species I would not read on Species II. Therefore, as Species I was elected, claims 1-7, 9-16, and 18-24 will be examined.
The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on December 15, 2023; February 13, 2025; May 14, 2026; and August 14, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner except as otherwise indicated.
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
5. Claims 1-3, 9-12, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al (US 2023/0335444 A1, hereafter Wang).
Regarding claim 1, Wang discloses a semiconductor device (Fig. 1A 100), comprising:
a plurality of source/drain regions (Fig. 1A 112) laterally disposed relative to one another in a row (Fig. 1A),
the plurality of source/drain regions (112) including two adjacent source/drain regions (Fig. 112a and 112d);
a plurality of source/drain region contacts (Fig. 1A 140) including two source/drain region contacts;
and a diffusion break (Fig. 1A 126) disposed between the two adjacent source/drain regions (112a and 112d) and extending toward a backside (top of Fig. 1A) of the semiconductor device (100).
Wang does not explicitly disclose the diffusion break extending between the two source/drain region contacts, the diffusion break including a different lateral dimension between the two adjacent source/drain regions than between the two source/drain region contacts.
However, Wang does disclose backside contacts can be connected to select source/drain regions ([0089]). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a backside contact connected to the adjacent source/drain region (112d, mirroring backside contact 140 on source/drain region 112a) to achieve the desired device application.
Furthermore, Wang with the backside source/drain contacts discloses the diffusion break (126) extending between the two source/drain region contacts (140), the diffusion break (126) including a different lateral dimension (Fig. 1A) between the two adjacent source/drain regions (112a and 112d) than between the two source/drain region contacts (140) (diffusion break 126 is rounded at end between the two source/drain region contacts, having a different lateral dimension at end compared to between the two adjacent source/drain regions).
Regarding claim 2, Wang discloses the semiconductor device as recited in claim 1, wherein the diffusion break (126) includes a portion (bottom part of 126 in Fig. 1A) that extends beyond the two adjacent source/drain regions (112a and 112d) opposite the backside of the semiconductor device (top of Fig. 1A).
Regarding claim 3, Wang discloses the semiconductor device as recited in claim 2, wherein the portion of the diffusion break (126) includes sidewall spacers (Fig. 2C 150).
Regarding claim 9, Wang discloses the semiconductor device as recited in claim 1, wherein the diffusion break (126) is disposed in a gate region (Fig. 1A 110+114) and the diffusion break (126) replaces a gate (Fig. 1A 110+114) (Fig. 2A-C, Fig. 4 410).
Regarding claim 10, Wang discloses the semiconductor device as recited in claim 1, wherein the diffusion break (126) is disposed in a device channel region (Fig. 1A 108) and the diffusion break (126) replaces a device channel (Fig. 1A 108) (Fig. 2A-C, Fig. 4 410).
Regarding claim 11, Wang discloses a semiconductor device (Fig. 1A 100), comprising:
a frontside (Fig. 1A bottom of 100) and a backside (Wang Fig. 1A top of 100) opposite the frontside (bottom of 100);
a plurality of source/drain regions (Fig. 1A 112) laterally disposed relative to one another, the plurality of source/drain regions (112) including two adjacent source/drain regions (Fig. 1A 112a and 112d);
a plurality of backside source/drain region contacts (Fig. 1A 140);
and a diffusion break (Fig. 1A 126) disposed between the two adjacent source/drain regions (112a and 112d) and having an upper portion (Fig. 1A bottom half of 126) and a lower portion (Fig. 1A top half of 126), the upper portion (bottom half of 126) being disposed in a gate region (Fig. 1A 110+114).
Wang does not explicitly disclose two backside source/drain region contacts respectively connected to the two adjacent source/drain regions from the backside, and the lower portion separating the two backside source/drain region contacts.
However, Wang does disclose backside contacts can be connected to select source/drain regions ([0089]). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a backside contact connected to the adjacent source/drain region (112d, mirroring backside contact 140 on source/drain region 112a) to achieve the desired device application.
Furthermore, Wang with the backside source/drain contacts discloses the lower portion of the diffusion break (bottom half of 126) separating the two backside source/drain region contacts (140).
Regarding claim 12, Wang discloses the semiconductor device as recited in claim 11, wherein the upper portion of the diffusion break (bottom half of 126) includes sidewall spacers (Fig. 2C 150).
Regarding claim 18, Wang discloses the semiconductor device as recited in claim 11, wherein the diffusion break (126) is disposed in the gate region (110+114) and the diffusion break (126) replaces a gate (Fig. 1A 110+114) (Fig. 2A-C, Fig. 4 410).
Regarding claim 19, Wang discloses the semiconductor device as recited in claim 11, wherein the diffusion break (126) is disposed in a device channel region (Fig. 1A 108) and the diffusion break (126) replaces a device channel (Fig. 1A 108) (Fig. 2A-C, Fig. 4 410).
6. Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 1 above, and further in view of Sung et al (US 2020/0020570 A1, hereafter Sung).
Regarding claim 4, Wang discloses the semiconductor device as recited in claim 1.
Wang does not disclose the diffusion break includes a wider portion between the two source/drain region contacts than between the two adjacent source/drain regions.
Sung discloses a diffusion break (Fig. 10 130) including a wider portion (bottom of 130) than [a portion] between the two adjacent source/drain regions (Fig. 10 122). Sung is analogous to Wang in the art of finFET and diffusion break structures.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the diffusion break shape of Wang with the shape of Sung to improve isolation of devices, as discussed by Sung ([0004]).
Furthermore, the device of Wang as modified by Sung discloses the wider portion between the two source/drain region contacts (Wang 140) than between the two adjacent source/drain regions (Wang 112a and 112d).
Regarding claim 5, Wang and Sung disclose the semiconductor device as recited in claim 4, wherein the wider portion of the diffusion break (Sung bottom part of 130) narrows (Sung Fig. 10) toward the two adjacent source/drain regions (Sung 122).
7. Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 1 above, and further in view of Yu et al (US 2023/0386971 A1, hereafter Yu).
Regarding claim 6, Wang discloses the semiconductor device as recited in claim 1, wherein the diffusion break (126) extends from a replacement metal gate layer (Fig. 1A 114).
Wang does not disclose the diffusion break extends to a backside power distribution network.
Yu discloses a backside power distribution network (Fig. 28A 174; [0092]). Yu is analogous to Wang in the art of finFET structure.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the backside power distribution network of Yu in the backside of the device of Wang to improve power delivery and efficiency in the desired device.
Furthermore, Wang with the backside power distribution network of Yu discloses the diffusion break (Wang 126) extends to a backside power distribution network (Yu 174).
Regarding claim 7, Wang and Yu disclose the semiconductor device as recited in claim 6, further comprising a backside interlevel dielectric layer (Wang Fig. 1A 119; Yu Fig. 28A 130) disposed between the backside power distribution network (Yu 174) and the diffusion break (Wang 138).
8. Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 11 above, and further in view of Sung.
Regarding claim 13, Wang discloses the semiconductor device as recited in claim 11.
Wang does not disclose the diffusion break includes a wider portion between the two backside source/drain region contacts than between the two adjacent source/drain regions.
Sung discloses a diffusion break (Fig. 10 130) including a wider portion (bottom of 130) than [a portion] between the two adjacent source/drain regions (Fig. 10 122).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the diffusion break shape of Wang with the shape of Sung to improve isolation of devices, as discussed by Sung ([0004]).
Furthermore, the device of Wang as modified by Sung discloses the wider portion between the two source/drain region contacts (Wang 140) than between the two adjacent source/drain regions (Wang 112a and 112d).
Regarding claim 14, Wang and Sung disclose the semiconductor device as recited in claim 13, wherein the wider portion of the diffusion (Sung bottom part of 130) break narrows (Sung Fig. 10) toward the two adjacent source/drain regions (Sung 122).
9. Claims 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 11 above, and further in view of Yu.
Regarding claim 15, Wang discloses the semiconductor device as recited in claim 11, wherein the diffusion break (126) extends from a replacement metal gate layer (Fig. 1A 114).
Wang does not disclose the diffusion break extends to a backside power distribution network.
Yu discloses a backside power distribution network (Fig. 28A 174; [0092]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the backside power distribution network of Yu in the backside of the device of Wang to improve power delivery and efficiency in the desired device.
Furthermore, Wang with the backside power distribution network of Yu discloses the diffusion break (Wang 126) extends to a backside power distribution network (Yu 174).
Regarding claim 16, Wang and Yu disclose the semiconductor device as recited in claim 15, further comprising a backside interlevel dielectric layer (Wang Fig. 1A 119; Yu Fig. 28A 130) disposed between the backside power distribution network (Yu 174) and the lower portion of the diffusion break (Wang top half of 138).
10. Claims 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Sung and Yun et al (US 2024/0290689 A1, hereafter Yun).
Regarding claim 20, Wang discloses a semiconductor device (Fig. 1A 100), comprising:
a frontside (Fig. 1A bottom of 100) and a backside (Wang Fig. 1A top of 100) opposite the frontside (bottom of 100);
a plurality of source/drain regions (Fig. 1A 112) laterally disposed relative to one another, the plurality of source/drain regions (112) including two adjacent source/drain regions (Fig. 1A 112a and 112d);
a plurality of backside source/drain region contacts (Fig. 1A 140);
and a diffusion break (Fig. 1A 126) disposed between the two adjacent source/drain regions (112a and 112d) and having an upper portion (Fig. 1A bottom half of 126) and a lower portion (Fig. 1A top half of 126),
the upper portion (bottom half of 126) being disposed in a gate region (Fig. 1A 110+114).
Wang does not explicitly disclose the plurality of backside source/drain region contacts including the two backside source/drain region contacts respectively connected to the two adjacent source/drain regions from the backside, and the lower portion separating the two backside source/drain region contacts.
However, Wang does disclose backside contacts can be connected to select source/drain regions ([0089]). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a backside contact connected to the adjacent source/drain region (112d, mirroring backside contact 140 on source/drain region 112a) to achieve the desired device application.
Furthermore, Wang with the backside source/drain contacts discloses the lower portion of the diffusion break (top half of 126) separating the two backside source/drain region contacts (140).
Wang also does not disclose the lower portion having a wider portion between the two backside source/drain region contacts than between the two adjacent source/drain regions.
Sung discloses the lower portion [of the diffusion break] having a wider portion (Fig. 10 130 bottom half).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the diffusion break shape of Wang with the shape of Sung to improve isolation of devices, as discussed by Sung ([0004]).
Furthermore, the device of Wang as modified by Sung discloses the wider portion between the two source/drain region contacts (Wang 140) than between the two adjacent source/drain regions (Wang 112a and 112d).
Wang and Sung do not disclose a contact area between respective ones of the two backside source/drain region contacts and corresponding ones of the two adjacent source/drain regions is increased.
Yun discloses a contact area (Fig. 2D side of 117 touching 130) between respective ones of the two backside source/drain region contacts (Fig. 2D 117) and corresponding ones of the two adjacent source/drain regions (Fig. 2D 130) is increased (side of contact 117 touching source/drain region 130 is greater than other sides of contact 117). Yun is analogous to Wang and Sung in the art of finFET structure.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the shape of the backside contacts in the device of Wang modified by Sung with the contact shape of Yun to improve power supply by maximizing area for conductivity and device performance.
Regarding claim 21, Wang, Sung and Yun disclose the semiconductor device as recited in claim 21, wherein the upper portion of the diffusion break (Wang bottom half of 126) includes sidewall spacers (Wang Fig. 2C 150).
11. Claims 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Sung and Yu.
Regarding claim 22, Wang discloses a semiconductor device (Fig. 1A 100), comprising:
a frontside (Fig. 1A bottom of 100) and a backside (Wang Fig. 1A top of 100) opposite the frontside (bottom of 100);
a plurality of source/drain regions (Fig. 1A 112) laterally disposed relative to one another, the plurality of source/drain regions (112) including two adjacent source/drain regions (Fig. 1A 112a and 112d);
a plurality of backside source/drain region contacts (Fig. 1A 140);
a diffusion break (Fig. 1A 126) disposed between the two adjacent source/drain regions (112a and 112d) and having an upper portion (Fig. 1A bottom half of 126) and a lower portion (Fig. 1A top half of 126), the upper portion (bottom half of 126) being disposed in a gate region (Fig. 1A 110+114);
and a backside interlevel dielectric layer (Wang Fig. 1A 119).
Wang does not explicitly disclose a plurality of backside source/drain region contacts (Fig. 1A 140) including two backside source/drain region contacts respectively connected to the two adjacent source/drain regions from the backside, and the lower portion separating the two backside source/drain region contacts.
However, Wang does disclose backside contacts can be connected to select source/drain regions ([0089]). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a backside contact connected to the adjacent source/drain region (112d, mirroring backside contact 140 on source/drain region 112a) to achieve the desired device application.
Furthermore, Wang with the backside source/drain contacts discloses the lower portion of the diffusion break (top half of 126) separating the two backside source/drain region contacts (140).
Wang also does not disclose the diffusion break including a wider portion between the two backside source/drain region contacts than between the two adjacent source/drain regions, the wider portion narrowing toward the two adjacent source/drain regions.
Sung discloses a diffusion break (Fig. 10 130) including a wider portion (bottom half of 130), the wider portion (bottom half of 130) narrowing toward the two adjacent source/drain regions (Fig. 10 122).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the diffusion break shape of Wang with the shape of Sung to improve isolation of devices, as discussed by Sung ([0004]).
Furthermore, the device of Wang as modified by Sung discloses the wider portion between the two source/drain region contacts (Wang 140) than between the two adjacent source/drain regions (Wang 112a and 112d).
Wang and Sung do not disclose a backside interlevel dielectric layer disposed between a backside power distribution network and the lower portion of the diffusion break.
Yu discloses a backside interlevel dielectric layer (Yu Fig. 28A 130) and a backside power distribution network (Yu 174).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the backside power distribution network of Yu in backside of the device of Wang and Sung to improve power delivery and efficiency in the desired device.
Furthermore, the device of Wang and Sung with the backside power distribution network of Yu discloses the backside interlevel dielectric layer (Wang 119; Yu 130) disposed between the backside power distribution network (Yu 174) and the lower portion of the diffusion break (Wang top half of 126).
Regarding claim 23, Wang, Sung, and Yu disclose the semiconductor device as recited in claim 22, wherein the upper portion of the diffusion break (Wang bottom half of 138) includes sidewall spacers (Wang Fig. 2C 150).
Regarding claim 24, Wang, Sung, and Yu disclose the semiconductor device as recited in claim 22, wherein the diffusion break (126) extends from a replacement metal gate layer (Fig. 1A 114) to the backside power distribution network (Yu 174).
Conclusion
12. The following art made of record and not relied upon is pertinent to applicant’s disclosure.
You et al (US 2025/0118657 A1) discloses a FET that has a through-via with a tapered shape that replaces a gate and a channel
Chen et al (US 2022/0157956 A1) discloses a finFET that has a backside contact with a variable shape
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL B SUN whose telephone number is (571)699-0231. The examiner can normally be reached Mon-Fri 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL B SUN/Examiner, Art Unit 2892
/ERIC W JONES/Primary Examiner, Art Unit 2892
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