DETAILED ACTION
IDS
All references provided in the IDS have been considered.
Election/Restrictions
Applicant’s election without traverse of Group 1 (claims 1-8, 19-20) in the reply filed on 03/02/2026 is acknowledged. Examiner notes the withdrawal of claims 9-18.
Specification
The disclosure is objected to because of the following informalities: missing or incorrect reference numerals.
In the specification, “a memory controller” is mentioned (for example, in ¶ [0273]), but no reference numerals are provided. Because “a memory controller” is claimed, a reference numeral should be provided. Appropriate correction is required.
In the specification, “a host” is mentioned (for example, in ¶ [0277]), but no reference numerals are provided. Because “a host” is claimed, a reference numeral should be provided. Appropriate correction is required.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “memory controller” and “host”, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a) because they fail to show the second insulating structure (element 230) as described in the specification. It is unclear from the drawings which components are contained within this structure. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 3 and 5 are objected to because of the following informalities:
Regarding claim 3,
Claim 3, line 8 recites “covering sidewall of the metal layer”. A suggested correction is “covering a sidewall of the metal layer”. Appropriate correction is required.
Regarding claim 5,
Claim 5, line 8 recites “and may cover a sidewalls of the”. A suggested corrections is “may cover a sidewall of the”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 3, 5, 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding Independent Claim 1, (and dependent claim(s) 2-8), recite(s) the limitation “a first insulating structure and a second insulating structure stacked in turn on the first semiconductor structure” in Claim 1, lines 3-4. The corresponding structure associated with the second insulating structure is not well-supported by the drawings and/or specification such that a determination of “stacked in turn” can be made. It has been interpreted to mean that at least a portion of the second insulating structure is above the first insulating structure. Claims 2-8 are rejected by virtue of their dependency on Claim 1. Appropriate correction is required.
Regarding Independent Claim 1, (and dependent claim(s) 2-8), recite(s) the limitation “a contact structure penetrating through the first insulating structure” in Claim 1, line 5. It is unclear how the contact structure penetrates through the first insulating structure. It has been interpreted to mean the contact structure contacts the first insulating structure. Claims 2-8 are rejected by virtue of their dependency on Claim 1. Appropriate correction is required.
Regarding Independent Claim 1, (and dependent claim(s) 2-8), recite(s) the limitation “a first electrode layer penetrating through at least part of the first insulating structure” in Claim 1, lines 7-8. It is unclear how the first electrode layer penetrates through the first insulating structure. It has been interpreted to mean the first electrode layer contacts the first insulating structure. Claims 2-8 are rejected by virtue of their dependency on Claim 1. Appropriate correction is required.
Regarding Independent Claim 1, (and dependent claim(s) 2-8), recite(s) the limitation “a second electrode layer penetrating through the second insulating structure” in Claim 1, lines 8-9. It is unclear how the second electrode layer penetrates through the second insulating structure. It has been interpreted to mean the second electrode layer contacts the second insulating structure. Claims 2-8 are rejected by virtue of their dependency on Claim 1. Appropriate correction is required.
Regarding Dependent Claim 3, recite(s) the limitation “the metal layer penetrates through the first support layer” in Claim 3, line 3. It is unclear how the metal layer penetrates through the first support layer. It has been interpreted to mean the metal layer contacts the first support layer. Claims 4 and 6 are rejected by virtue of their dependency on Claim 3. Appropriate correction is required.
Regarding Dependent Claim 3, recite(s) the limitation “the semiconductor layer is located between the semiconductor layer and the metal layer” in Claim 3, line 5. It is unclear how a layer can be between itself. It has been interpreted to mean the semiconductor layer is located between the first semiconductor structure and the metal layer. Claims 4 and 6 are rejected by virtue of their dependency on Claim 3. Appropriate correction is required.
Regarding Dependent Claim 5, recite(s) the limitation “the metal layer penetrates through the first support layer” in Claim 5, line 3. It is unclear how the metal layer penetrates through the first support layer. It has been interpreted to mean the metal layer contacts the first support layer. Appropriate correction is required.
Regarding Dependent Claim 5, recite(s) the limitation “the semiconductor layer is located between the semiconductor layer and the metal layer” in Claim 5, line 5. It is unclear how a layer can be between itself. It has been interpreted to mean the semiconductor layer is located between the first semiconductor structure and the metal layer. Appropriate correction is required.
Regarding Independent Claim 19, recite(s) the limitation “a first insulating structure and a second insulating structure stacked in turn on the first semiconductor structure” in Claim 19, lines 4-5. The corresponding structure associated with the second insulating structure is not well-supported by the drawings and/or specification such that a determination of “stacked in turn” can be made. It has been interpreted to mean that at least a portion of the second insulating structure is above the first insulating structure. Appropriate correction is required.
Regarding Independent Claim 19, recite(s) the limitation “a contact structure penetrating through the first insulating structure” in Claim 19, line 6. It is unclear how the contact structure penetrates through the first insulating structure. It has been interpreted to mean the contact structure contacts the first insulating structure. Appropriate correction is required.
Regarding Independent Claim 19, recite(s) the limitation “a first electrode layer penetrating through at least part of the first insulating structure” in Claim 19, lines 8-9. It is unclear how the first electrode layer penetrates through the first insulating structure. It has been interpreted to mean the first electrode layer contacts the first insulating structure. Appropriate correction is required.
Regarding Independent Claim 19, recite(s) the limitation “a second electrode layer penetrating through the second insulating structure” in Claim 19, lines 9-10. It is unclear how the second electrode layer penetrates through the second insulating structure. It has been interpreted to mean the second electrode layer contacts the second insulating structure. Appropriate correction is required.
Regarding Independent Claim 20, recite(s) the limitation “a first insulating structure and a second insulating structure stacked in turn on the first semiconductor structure” in Claim 20, lines 5-6. The corresponding structure associated with the second insulating structure is not well-supported by the drawings and/or specification such that a determination of “stacked in turn” can be made. It has been interpreted to mean that at least a portion of the second insulating structure is above the first insulating structure. Appropriate correction is required.
Regarding Independent Claim 20, recite(s) the limitation “a contact structure penetrating through the first insulating structure” in Claim 20, line 7. It is unclear how the contact structure penetrates through the first insulating structure. It has been interpreted to mean the contact structure contacts the first insulating structure. Appropriate correction is required.
Regarding Independent Claim 20, recite(s) the limitation “a first electrode layer penetrating through at least part of the first insulating structure” in Claim 20, lines 9-10. It is unclear how the first electrode layer penetrates through the first insulating structure. It has been interpreted to mean the first electrode layer contacts the first insulating structure. Appropriate correction is required.
Regarding Independent Claim 20, recite(s) the limitation “a second electrode layer penetrating through the second insulating structure” in Claim 19, lines 10-11. It is unclear how the second electrode layer penetrates through the second insulating structure. It has been interpreted to mean the second electrode layer contacts the second insulating structure. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hua (CN 116193853 A).
Re: Independent Claim 1, Hua discloses:
A memory (Hua, pg. 5), comprising:
a first semiconductor structure (Hua, isolation structure, highly-doped layer, substrate; Fig. 4, elements 120, 103, and 100, respectively, make up the first semiconductor structure) comprising a vertical transistor (Hua, channel column, gate structure, first source/drain doped region, second source/drain doped region; Fig.4, elements 101, 102, 121, 122, respectively, make up the vertical transistor, pg. 5, ¶ [0011]);
a first insulating structure (Hua, insulating layer; Figs. 2 and 4, element 105, the rectangular region containing element 105, see attached annotated figure, can be considered a first insulating structure) and a second insulating structure (Hua, the rectangular region containing element 116 can be considered a second insulating structure, see attached
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annotated figure) stacked in turn on the first semiconductor structure;
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a contact structure (Hua, second highly-doped layer; Fig. 4, element 104 and the small rectangular region (metal silicide layer, not numbered, above it can be considered the contact structure, pg. 6, ¶ [0001]) penetrating through the first insulating structure and connected with a semiconductor body (Hua, channel column and second source/drain doped region; Fig. 4, elements 101 and 122, respectively, are a semiconductor body) of the vertical transistor;
a first electrode structure (Hua, first electrode layer and second electrode layer; Fig. 4, elements 111 and 117, respectively, make up a first electrode structure) comprising a first electrode layer (Hua, first electrode layer; Fig. 4, element 111) penetrating through at least part of the first insulating structure (Hua, Fig. 4 shows a portion of 111 within 105) and a second electrode layer (Hua, second electrode layer; Fig. 4, element 117) penetrating through the second insulating structure (Hua, Fig. 4 shows element 117 within element 116), the first electrode layer covering a sidewall of at least part of the contact structure and being connected with the contact structure (Hua, Fig. 4 shows element 111 touching the upper surface (which can be considered a sidewall) of the contact structure), and the second electrode layer being connected with the first electrode layer (Hua, Fig. 4 shows 117 and 111 are connected through layer 116);
a second electrode structure (Hua, first pillar layer and second pillar layer; Fig. 4, elements 112 and 118, respectively make up a second electrode structure) comprising a first part (Hua, first pillar layer; Fig. 4, element 112) in the first insulating structure (Hua, Fig. 4 shows a portion of 112 within the region containing 105) and a second part (Hua, second pillar layer; Fig. 4, element 118) in the second insulating structure (Hua, Fig. 4 shows element 118 in the region containing element 116), the first part covering a sidewall of part of the first electrode layer (Hua, Fig. 4 shows element 112 covering a sidewall of element 111), and the second part covering a sidewall of part of the second electrode layer (Hua, Fig. 4 shows element 118 covering a sidewall of 117);
and a capacitor dielectric layer (Hua, dielectric layer; Fig. 4, element 116) between the first electrode structure and the second electrode structure (Hua, Fig. 4 shows element 116 between elements 111 and 117, the first electrode structure, and between elements 112 and 118, the second electrode structure).
Re: Dependent Claim 2, Hua disclose(s) all the limitations of claim 1 on which this claim depends. Hua further discloses:
wherein:
the first insulating structure (Hua, the rectangular region containing element 105, see attached annotated figure, can be considered a first insulating structure) comprises a first insulating layer (Hua, insulating layer; Fig. 2, element 105) and a first support layer (Hua, first sacrificial layer; Fig. 2, element 106) stacked in turn on the first semiconductor structure (Hua, isolation structure, highly-doped layer, substrate; Fig. 4, elements 120, 103, and 100, respectively, make up the first semiconductor structure),
the first insulating layer is disposed as being spaced apart from the first support layer (Hua, Fig. 2 shows elements 105 and 106 as separate layers, therefore they are spaced apart), and the first part (Hua, first pillar layer; Fig. 4, element 112) is located between the first insulating layer and the first support layer (Hua, Fig. 2).
Re: Dependent Claim 3, Hua disclose(s) all the limitations of claim 2 on which this claim depends. Hua further discloses:
wherein:
the contact structure (Hua, second highly-doped layer; Fig. 4, element 104 and the small rectangular region (metal silicide layer, not numbered, above it can be considered the contact structure, pg. 6, ¶ [0001]) comprises a metal layer (Hua, metal silicide layer, electrode layer, first support layer; Fig. 4, not numbered, pg. 6, ¶ [0001], element 111 and 107, respectively, make up a metal layer) and a semiconductor layer (Hua, second highly doped layer; Fig. 4, element 104, pg. 7, ¶ [0012]),
the metal layer penetrates through the first support layer (Hua, first sacrificial layer; Fig. 2, element 106) and extends into the first insulating layer (Hua, insulating layer; Fig. 2, element 105),
the semiconductor layer is located between the semiconductor layer and the metal layer (Hua, Fig. 2, shows element 104 between the metal layer and the semiconductor structure, where isolation structure, highly-doped layer, substrate; Fig. 2, elements 120, 103, and 100, respectively, make up the first semiconductor structure),
and
the first electrode layer (Hua, first electrode layer; Fig. 4, element 111) comprises a first sub-electrode layer (Hua, first electrode layer; Fig. 4, element 111, the vertical portion of 111 directly over the contact structure can be considered a first sub-electrode layer) over the semiconductor layer and covering sidewall of the metal layer (Hua, Fig. 4 shows the vertical portion of 111 directly over element 104, and covers a sidewall of 107).
Re: Dependent Claim 4, Hua disclose(s) all the limitations of claim 3 on which this claim depends. Hua further discloses:
wherein the first electrode layer (Hua, first electrode layer; Fig. 4, element 111) further comprises a second sub- electrode layer (Hua, first electrode layer; Fig. 4, element 111, the horizontal portion of 111 contained within layer 105, can be considered a second sub-electrode layer) between the semiconductor layer and the metal layer.
Re: Dependent Claim 5, Hua disclose(s) all the limitations of claim 2 on which this claim depends. Hua further discloses:
wherein:
the contact structure (Hua, second highly-doped layer; Fig. 2, element 104 and the small rectangular region (metal silicide layer, not numbered, above it can be considered the contact structure, pg. 6, ¶ [0001]) comprises a metal layer (Hua, metal silicide layer, electrode layer, first support layer; Fig. 2, not numbered, pg. 6, ¶ [0001], element 111 and 107, respectively, make up a metal layer) and a semiconductor layer (Hua, second highly doped layer; Fig. 2, element 104, pg. 7, ¶ [0012]),
the metal layer penetrates through the first support layer (Hua, first sacrificial layer; Fig. 2, element 106, a portion of 111 is in contact with layer 106) and extends to between the first insulating layer (Hua, insulating layer; Fig. 2, element 105) and the first support layer (Hua, Fig. 2, shows a portion of 111 extending between 105 and 106),
the semiconductor layer is located between the semiconductor layer and the metal layer (Hua, Fig. 2, shows element 104 between the metal layer and the semiconductor structure, where isolation structure, highly-doped layer, substrate; Fig. 2, elements 120, 103, and 100, respectively, make up the first semiconductor structure),
and
the first electrode layer (Hua, first electrode layer; Fig. 4, element 111) is located over the first semiconductor structure and may cover a sidewalls of the semiconductor layer and the metal layer (Hua, Fig. 2 shows element 111 over 104 and the metal silicide layer (not numbered, which is covering a sidewall of the semiconductor and metal layers).
Re: Dependent Claim 6, Hua disclose(s) all the limitations of claim 3 on which this claim depends. Hua further discloses:
wherein the contact structure (Hua, second highly-doped layer; Fig. 2, element 104 and the small rectangular region (metal silicide layer, not numbered, above it can be considered the contact structure, pg. 6, ¶ [0001]) comprises a connection layer (Hua, metal silicide layer (region formed above element 104); Fig. 2, not numbered, pg. 6, ¶ [0001], can be considered a connection layer) between the semiconductor layer (Hua, second highly doped layer; Fig. 2, element 104, pg. 7, ¶ [0012]) and the metal layer (Hua, metal silicide layer, electrode layer, first support layer; Fig. 2, not numbered, pg. 6, ¶ [0001], element 111 and 107, respectively, make up a metal layer) (Hua, Fig.2 shows that the metal silicide layer is between 104 and a portion of the metal layer).
Re: Dependent Claim 7, Hua disclose(s) all the limitations of claim 1 on which this claim depends. Hua further discloses:
wherein:
the second insulating structure (Hua, the rectangular region containing element 116 can be considered a second insulating structure, see attached annotated figure) comprises a second support layer (Hua, first support layer; Fig. 4, element 107, the leftmost portion),
the second support layer is disposed as being spaced apart from the first insulating structure (Hua, insulating layer; Figs. 2 and 4, element 105, the rectangular region containing element 105, see attached annotated figure, can be considered a first insulating structure, element 107 is separate from the first insulating structure), and
the second part (Hua, second pillar layer; Fig. 4, element 118) is located between the first insulating structure and the second support layer (Hua, Fig. 4 shows element 118 is between the first insulating structure and the second support layer).
Re: Dependent Claim 8, Hua disclose(s) all the limitations of claim 7 on which this claim depends. Hua further discloses:
wherein:
the second insulating structure (Hua, the rectangular region containing element 116 can be considered a second insulating structure, see attached annotated figure) further comprises a third support layer (Hua, second support layer; Fig. 4, element 109, leftmost portion),
the third support layer is disposed as being spaced apart from the second support layer (Hua, first support layer; Fig. 4, element 107, the leftmost portion),
and
the second part (Hua, second pillar layer; Fig. 4, element 118) is further located between the second support layer and the third support layer (Hua, Fig. 4, shows element 118 between 107 and 109 in a vertical direction).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hua (CN 116193853 A) in view of Saito (US 20260101500 A1).
Re: Independent Claim 19, Hua discloses:
A memory system (Hua, Fig. 4), comprising:
a memory (Hua, Fig. 4, pg. 5), comprising:
a first semiconductor structure (Hua, isolation structure, highly-doped layer, substrate; Fig. 4, elements 120, 103, and 100, respectively, make up the first semiconductor structure) comprising a vertical transistor (Hua, channel column, gate structure, first source/drain doped region, second source/drain doped region; Fig.4, elements 101, 102, 121, 122, respectively, make up the vertical transistor, pg. 5, ¶ [0011]);
a first insulating structure (Hua, insulating layer; Figs. 2 and 4, element 105, the rectangular region containing element 105, see attached annotated figure of claim 1, can be considered a first insulating structure) and a second insulating structure (Hua, the rectangular region containing element 116 can be considered a second insulating structure, see attached annotated figure of claim 1) stacked in turn on the first semiconductor structure;
a contact structure (Hua, second highly-doped layer; Fig. 4, element 104 and the small rectangular region (metal silicide layer, not numbered, above it can be considered the contact structure, pg. 6, ¶ [0001]) penetrating through the first insulating structure and connected with a semiconductor body (Hua, channel column and second source/drain doped region; Fig. 4, elements 101 and 122, respectively, are a semiconductor body) of the vertical transistor;
a first electrode structure (Hua, first electrode layer and second electrode layer; Fig. 4, elements 111 and 117, respectively, make up a first electrode structure) comprising a first electrode layer (Hua, first electrode layer; Fig. 4, element 111) penetrating through at least part of the first insulating structure (Hua, Fig. 4 shows a portion of 111 within 105) and a second electrode layer (Hua, second electrode layer; Fig. 4, element 117) penetrating through the second insulating structure (Hua, Fig. 4 shows element 117 within element 116), the first electrode layer covering a sidewall of at least part of the contact structure and being connected with the contact structure (Hua, Fig. 4 shows element 111 touching the upper surface (which can be considered a sidewall) of the contact structure), and the second electrode layer being connected with the first electrode layer (Hua, Fig. 4 shows 117 and 111 are connected through layer 116);
a second electrode structure (Hua, first pillar layer and second pillar layer; Fig. 4, elements 112 and 118, respectively make up a second electrode structure) comprising a first part (Hua, first pillar layer; Fig. 4, element 112) in the first insulating structure (Hua, Fig. 4 shows a portion of 112 within the region containing 105) and a second part (Hua, second pillar layer; Fig. 4, element 118) in the second insulating structure (Hua, Fig. 4 shows element 118 in the region containing element 116), the first part covering a sidewall of part of the first electrode layer (Hua, Fig. 4 shows element 112 covering a sidewall of element 111), and the second part covering a sidewall of part of the second electrode layer (Hua, Fig. 4 shows element 118 covering a sidewall of 117);
and a capacitor dielectric layer (Hua, dielectric layer; Fig. 4, element 116) between the first electrode structure and the second electrode structure (Hua, Fig. 4 shows element 116 between elements 111 and 117, the first electrode structure, and between elements 112 and 118, the second electrode structure).
Hua is silent regarding:
and a memory controller coupled to the memory and configured to control the memory.
Saito discloses:
and a memory controller (Saito, memory controller; Figs. 21A and 21B, element 1214) coupled to the memory (Saito, DRAM, Figs. 21A and 21B, element 1221) and configured to control the memory (Saito, ¶ [0404]);
Hua discloses a memory system comprising a memory, but does not disclose this memory to be coupled to a memory controller to be configured to control the memory. Saito discloses a storage device which includes a memory, memory system, and electronic device. Both disclose the use of a memory with a vertical transistor, semiconductor structures, electrodes, and insulating structures and are therefore analogous art. It would have been obvious to a POSITA before the effective filing date to include a memory controller and host coupled to the memory system as an interface to the memory (Saito, ¶ [0404]).
Re: Independent Claim 20, Hua discloses:
An electronic device (Hua, Fig. 4), comprising:
a memory system (Hua, Fig. 4), comprising:
a memory (Hua, Fig. 4, pg. 5), comprising:
a first semiconductor structure (Hua, isolation structure, highly-doped layer, substrate; Fig. 4, elements 120, 103, and 100, respectively, make up the first semiconductor structure) comprising a vertical transistor (Hua, channel column, gate structure, first source/drain doped region, second source/drain doped region; Fig.4, elements 101, 102, 121, 122, respectively, make up the vertical transistor, pg. 5, ¶ [0011]);
a first insulating structure (Hua, insulating layer; Figs. 2 and 4, element 105, the rectangular region containing element 105, see attached annotated figure of claim 1, can be considered a first insulating structure) and a second insulating structure (Hua, the rectangular region containing element 116 can be considered a second insulating structure, see attached annotated figure of claim 1) stacked in turn on the first semiconductor structure;
a contact structure (Hua, second highly-doped layer; Fig. 4, element 104 and the small rectangular region (metal silicide layer, not numbered, above it can be considered the contact structure, pg. 6, ¶ [0001]) penetrating through the first insulating structure and connected with a semiconductor body (Hua, channel column and second source/drain doped region; Fig. 4, elements 101 and 122, respectively, are a semiconductor body) of the vertical transistor;
a first electrode structure (Hua, first electrode layer and second electrode layer; Fig. 4, elements 111 and 117, respectively, make up a first electrode structure) comprising a first electrode layer (Hua, first electrode layer; Fig. 4, element 111) penetrating through at least part of the first insulating structure (Hua, Fig. 4 shows a portion of 111 within 105) and a second electrode layer (Hua, second electrode layer; Fig. 4, element 117) penetrating through the second insulating structure (Hua, Fig. 4 shows element 117 within element 116), the first electrode layer covering a sidewall of at least part of the contact structure and being connected with the contact structure (Hua, Fig. 4 shows element 111 touching the upper surface (which can be considered a sidewall) of the contact structure), and the second electrode layer being connected with the first electrode layer (Hua, Fig. 4 shows 117 and 111 are connected through layer 116);
a second electrode structure (Hua, first pillar layer and second pillar layer; Fig. 4, elements 112 and 118, respectively make up a second electrode structure) comprising a first part (Hua, first pillar layer; Fig. 4, element 112) in the first insulating structure (Hua, Fig. 4 shows a portion of 112 within the region containing 105) and a second part (Hua, second pillar layer; Fig. 4, element 118) in the second insulating structure (Hua, Fig. 4 shows element 118 in the region containing element 116), the first part covering a sidewall of part of the first electrode layer (Hua, Fig. 4 shows element 112 covering a sidewall of element 111), and the second part covering a sidewall of part of the second electrode layer (Hua, Fig. 4 shows element 118 covering a sidewall of 117);
and a capacitor dielectric layer (Hua, dielectric layer; Fig. 4, element 116) between the first electrode structure and the second electrode structure (Hua, Fig. 4 shows element 116 between elements 111 and 117, the first electrode structure, and between elements 112 and 118, the second electrode structure)
Hua is silent regarding:
and a memory controller coupled to the memory and configured to control the memory; and
a host coupled to the memory system.
Saito discloses:
and a memory controller (Saito, memory controller; Figs. 21A and 21B, element 1214) coupled to the memory (Saito, DRAM, Figs. 21A and 21B, element 1221) and configured to control the memory (Saito, ¶ [0404]);
and
a host (Saito, CPU; Figs. 21A and 21B, element 1211) coupled to the memory system (Saito, GPU module; Figs. 21A and 21B, element 1204, ¶ [0401 - 0409]).
Hua discloses a memory system comprising a memory, but does not disclose this memory to be coupled to a memory controller to be configured to control the memory and a host coupled to the memory system. Saito discloses a storage device which includes a memory, memory system, and electronic device. Both disclose the use of a memory with a vertical transistor, semiconductor structures, electrodes, and insulating structures and are therefore analogous art. It would have been obvious to a POSITA before the effective filing date to include a memory controller and host coupled to the memory system for suitable computations of a large number of pieces of data and therefore image processing or product-sum operation (Saito, ¶ [0401]).
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
Yamazaki (US 20130221356 A1) and Inaba (US 20250344565 A1), disclose relevant features such as memory devices, vertical transistors, electronic devices, memory systems, semiconductor structures and are therefore considered pertinent to the current application.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIMARTA KAUR CHOWDHARY whose telephone number is (571)272-7679. The examiner can normally be reached usually Monday - Thursday, 6:45 AM - 4:45 PM (EST).
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/NIMARTA KAUR CHOWDHARY/ Examiner, Art Unit 2898
/Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898
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