DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-6, and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Haeberlen (U.S. PGPub 2017/0373180).
Regarding claim 1, Haeberlen teaches a trench MOSFET ([0091]) comprising a substrate having a first doping type; an epitaxial layer having the first doping type, located on the substrate; gate trenches and a first conductive channel, extending from a surface to an inside of the epitaxial layer, the gate trenches being located on two sides of the first conductive channel and symmetrically distributed with respect to the first conductive channel; gate conductors, each located in one of the gate trenches and isolated from the epitaxial layer via a gate dielectric layer; an epitaxial depletion region having a second doping type, located in the epitaxial layer at a bottom of the first conductive channel; body regions having the second doping type, located on two sides of each gate trench and adjacent to a side wall of the first conductive channel; source regions having the first doping type, each located on each of the body region; a source electrode, contacting the epitaxial depletion region via the first conductive channel; and a drain electrode, contacting the substrate on a surface of the substrate away from the epitaxial layer (Fig. 6, substrate 41, epitaxial layer 40, gate trenches 10, first conductive channel 21, gate conductors 11, gate dielectric 12, epitaxial depletion 20, body regions 50, source regions 80, source electrode 60, drain electrode 42 ([0087]-[0089], [0044]-[0045]).
Regarding claim 4, Haeberlen teaches wherein a thickness of the gate dielectric layer at a bottom of the gate trenches is not smaller than a thickness of the gate dielectric layer on a side wall of the gate trenches (Fig. 6).
Regarding claim 5, Haeberlen teaches an interlayer dielectric layer; wherein the gate conductor is isolated from the source electrode via the interlayer dielectric layer (70, [0058]).
Regarding claim 6, Haeberlen teaches a method for manufacturing a trench MOSFET, comprising: forming an epitaxial layer having a first doping type on a substrate having the first doping type; forming gate trenches extending from a surface to an inside of the epitaxial layer; forming a gate conductor and a gate dielectric layer inside each of the gate trenches, the gate conductor being isolated from the epitaxial layer via the gate dielectric layer; forming body regions having a second doping type, the body regions being located on two sides of each gate trench; forming source regions having the first doping type, each of the source regions being located in each of the body regions; forming a first conductive channel extending from the surface to the inside of the epitaxial layer between two of the gate trenches, the two gate trenches being symmetrically distributed with respect to the first conductive channel; forming an epitaxial depletion region having the second doping type, the epitaxial depletion region being located in the epitaxial layer at a bottom of the first conductive channel; forming a source electrode, the source electrode contacting the epitaxial depletion region via the first conductive channel; and forming a drain electrode, the drain electrode contacting the substrate on a surface of the substrate away from the epitaxial layer (Fig. 6, substrate 41, epitaxial layer 40, gate trenches 10, first conductive channel 21, gate conductors 11, gate dielectric 12, epitaxial depletion 20, body regions 50, source regions 80, source electrode 60, drain electrode 42 ([0087]-[0089], [0098], [0044]-[0045]).
Regarding claim 9, Haeberlen teaches wherein a thickness of the gate dielectric layer at a bottom of the gate trenches is not smaller than a thickness of the gate dielectric layer on a side wall of the gate trenches (Fig. 6).
Regarding claim 10, Haeberlen teaches an interlayer dielectric layer; wherein the gate conductor is isolated from the source electrode via the interlayer dielectric layer (70, [0058]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Haeberlen (U.S. PGPub 2017/0373180) in view of Zeng (U.S. PGPub 2012/0043602).
Regarding claim 2, Haeberlen does not explicitly teach wherein the epitaxial depletion region is formed by multiple ion implantations.
Zeng teaches wherein forming a doped region is formed at the base of a trench by ion implantation, which can comprise multiple implant steps (Fig. 8, [0026]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Zeng with Haeberlen such that the epitaxial depletion region is formed by multiple ion implantations for the purpose of performing the ion implantation process of Haeberlen according to a method known in the art (Haeberlen, [0098]; Zeng, [0026]).
Regarding claim 7, Haeberlen does not explicitly teach wherein the epitaxial depletion region is formed by multiple ion implantations.
Zeng teaches wherein forming a doped region is formed at the base of a trench by ion implantation, which can comprise multiple implant steps (Fig. 8, [0026]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Zeng with Haeberlen such that the epitaxial depletion region is formed by multiple ion implantations for the purpose of performing the ion implantation process of Haeberlen according to a method known in the art (Haeberlen, [0098]; Zeng, [0026]).
Claims 3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Haeberlen (U.S. PGPub 2017/0373180) in view of Long (U.S. PGPub 2011/0284953).
Regarding claim 3, Haeberlen does not explicitly teach second conductive channels, wherein the source electrode contacts the gate conductor via the second conductive channel.
Long teaches conductive channels connecting a source electrode to trench gate conductors (Fig. 3, 61, 42, 70, [0024]-[0026]).
Therefore it would have been obvious to a person having ordinary skill in the art to combine the teachings of Long with Haeberlen such that the device comprises second conductive channels, wherein the source electrode contacts the gate conductor via the second conductive channel for the purpose of providing contacts to the gate of the MOSFET (Long, [0026]).
Regarding claim 8, Haeberlen does not explicitly teach forming second conductive channels, wherein the source electrode contacts the gate conductor via the second conductive channel.
Long teaches conductive channels connecting a source electrode to trench gate conductors (Fig. 3, 61, 42, 70, [0024]-[0026]).
Therefore it would have been obvious to a person having ordinary skill in the art to combine the teachings of Long with Haeberlen such that the device comprises forming second conductive channels, wherein the source electrode contacts the gate conductor via the second conductive channel for the purpose of providing contacts to the gate of the MOSFET (Long, [0026]).
Conclusion
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/ALIA SABUR/Primary Examiner, Art Unit 2812