Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 10-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by He et al. (US Pub. No. 2022/0335982 A1), hereafter referred to as He.
As to claim 1, He discloses a memory device (figs 2-3, [0028]), comprising:
a horizontally oriented access device ([0030]) having a first source/drain region (fig 2, 221) and a second source/drain region (223) separated by a channel region (225), the access device being operatively controlled by a gate (207-1);
a hybrid gate dielectric (304; [0040] a combination of the materials is a hybrid gate dielectric) separating the gate (307) from the channel region (325); and
a horizontally oriented storage node ([0031]) coupled to the second source/drain region (223) of the access device ([0030]).
As to claim 2, He discloses the memory device of claim 1 (paragraphs above),
wherein the hybrid gate dielectric is a multi-layer dielectric having a first dielectric material and a second dielectric material ([0040] sub-layer create multi-layer dielectric wherein multiple dielectric materials are taught).
As to claim 10, He discloses the memory device of claim 1 (paragraphs above),
wherein the gate is a horizontally oriented gate (fig 2, 207-1), and the first source/drain region (221) is coupled to a vertically oriented digit line (203; [0034]).
As to claim 11, He discloses the memory device of claim 1 (paragraphs above),
wherein the access device is a thin film transistor ([0023]; [0172]) and the storage node is a horizontally oriented capacitor ([0031]).
As to claim 12, He discloses a memory device (fig 2), comprising:
a horizontally oriented access device ([0030]) having a first source/drain region (221) and a second source/drain region (223) separated by a channel region (225), the access device being operatively controlled by a gate (207) opposing the channel region (225);
a multi-layer gate dielectric (fig 3A, [0037]; [0040] multi-layer 304 wherein half of 304 closest to channel 325 is a first layer and half of 304 away from channel 325 is a second layer) having a first dielectric material ([0040]) and a second dielectric material ([0040]) separating the gate (307) from the channel region (325), the second dielectric material being different from the first dielectric material ([0040]);
a horizontally oriented storage node (227) coupled to the second source/drain region (223) of the access device ([0030]); and
a vertically oriented digit line (203; [0034]) coupled to the first source/drain region (221) of the access device ([0030]).
As to claim 13, He discloses the memory device of claim 12 (paragraphs above),
wherein the gate is a gate all around ([0044]) structure separated from the channel region (325) by the multi-layer gate dielectric (304).
As to claim 14, He discloses the memory device of claim 12 (paragraphs above),
wherein the storage node is located in a same plane horizontally with the horizontally oriented access device (227 and 225).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3-6, 9, 15-18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over He et al. (US Pub. No. 2022/0335982 A1), hereafter referred to as He, in view of Ma et al. (US Pub. No. 2002/0130340 A1), hereafter referred to as Ma.
As to claim 3, He discloses the memory device of claim 1 (paragraphs above).
He does not disclose the hybrid gate dielectric material, comprising:
a first layer having a surface formed in contact with the channel region;
a second layer having a surface formed in contact with a surface of the first layer opposite the first layer surface formed in contact with the channel region;
a third layer having a surface formed in contact with a surface of the second layer opposite the second layer surface formed in contact with the surface of the first layer; and
wherein the gate is formed in contact with a surface of the third layer opposite the third layer surface formed in contact with the surface of the second layer.
Nonetheless, Ma discloses a transistor structure comprising a hybrid multi-layer gate dielectric material (fig 2, 116; [0033]), comprising:
a first layer (130) having a surface formed in contact with a channel region (114);
a second layer (140) having a surface formed in contact with a surface of the first layer (130) opposite the first layer surface formed in contact with the channel region (114);
a third layer (150) having a surface formed in contact with a surface of the second layer (140) opposite the second layer surface formed in contact with the surface of the first layer (130); and
wherein a gate (118) is formed in contact with a surface of the third layer (150) opposite the third layer surface formed in contact with the surface of the second layer (140).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the gate dielectric of He with the layer stack taught by Ma since this will decrease leakage currents.
As to claim 4, He in view of Ma disclose the memory device of claim 3 (paragraphs above).
Ma further discloses wherein the first layer is formed of a first dielectric material, the second layer is a second dielectric material, and the third layer is formed of the first dielectric material ([0033]).
As to claim 5, He in view of Ma disclose the memory device of claim 4 (paragraphs above).
Ma further discloses wherein the first dielectric material is a silicon dioxide (SiO2) dielectric material ([0033]), and the second dielectric material is a high-k dielectric material ([0033]), however, Ma does not teach an aluminum oxide (AlOx) dielectric material as the high-k dielectric material, nonetheless, He discloses aluminum oxide as a high-k dielectric material ([0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the interfacial layers of Ma surrounding the high-k dielectric material taught by He since this will provide an optimized EOT for transistor.
As to claim 6, He in view of Ma disclose the memory device of claim 4 (paragraphs above).
Ma further discloses wherein the second dielectric material is a dielectric material having an atomic composition with a fixed negative charge density of at least -1e12/cm2 ([0033])
As to claim 9, He in view of Ma disclose the memory device of claim 3 (paragraphs above).
He further discloses wherein the gate is a gate all around ([0044]) structure opposing the channel region (325).
As to claim 15, He discloses a method of forming vertical 3D memory (figs 2 and 12-13; [0016]), comprising:
forming a first horizontally oriented thin film transistor in a first horizontal tier of a multi-tier 3D memory (fig 12C, first tier including thin-film semiconductor layer 1232-1), the first TFT having a first source/drain region (1275) and a second source/drain region (1278) separated by a channel region (1232-1);
forming a gate dielectric (1238) separating a gate (1277) from the channel region (1232-1) to form an access device ([0030]);
forming a horizontally oriented storage node (fig 13C [0147]) coupled to the second source/drain region (1378) of the access device; and
forming a vertically oriented digit line ([0143]) coupled to the first source/drain region (1278) of the access device ([0030]).
He does not disclose forming a multi-layer gate dielectric, having a first dielectric material as a first layer and a second dielectric material as a second layer, the second dielectric material being different from the first dielectric material.
Nonetheless, Ma discloses a multi-layer gate dielectric (fig 2, 116; [0033]), having a first dielectric material as a first layer and a second dielectric material as a second layer, the second dielectric material being different from the first dielectric material ([0033]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the gate dielectric of He with the layer stack taught by Ma since this will decrease leakage currents.
As to claim 16, He in view of Ma disclose the method of claim 15 (paragraphs above).
Ma further discloses a transistor structure comprising forming multi-layer gate dielectric material (fig 2, 116; [0033]), comprising:
forming a first layer (130) having a surface formed in contact with a channel region (114);
forming a second layer (140) having a surface formed in contact with a surface of the first layer (130) opposite the first layer surface formed in contact with the channel region (114);
forming a third layer (150) having a surface formed in contact with a surface of the second layer (140) opposite the second layer surface formed in contact with the surface of the first layer (130); and
wherein a gate (118) is formed in contact with a surface of the third layer (150) opposite the third layer surface formed in contact with the surface of the second layer (140).
As to claim 17, He in view of Ma disclose the method of claim 15 (paragraphs above).
Ma further discloses wherein the first dielectric material is a silicon dioxide (SiO2) dielectric material ([0033]), and the second dielectric material is a high-k dielectric material ([0033]), however, Ma does not teach an aluminum oxide (AlOx) dielectric material as the high-k dielectric material, nonetheless, He discloses aluminum oxide as a high-k dielectric material ([0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the interfacial layers of Ma surrounding the high-k dielectric material taught by He since this will provide an optimized EOT for transistor.
As to claim 18, He in view of Ma disclose the method of claim 15 (paragraphs above).
Ma further discloses forming the second dielectric material of a dielectric material having an atomic composition with a fixed negative charge density of at least -1e12/ cm2 ([0033]).
As to claim 20, He in view of Ma disclose the method of claim 15 (paragraphs above).
He further discloses forming the gate as a gate all around ([0044]) structure separated from the channel region (325) by the multi-layer gate dielectric (304).
Allowable Subject Matter
Claims 7-8 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach or suggest wherein the second layer has a vertical thickness (t2) which is less than a vertical thickness (t1) of the first layer and is less than a vertical thickness (t3) of the third layer, as recited in claim 7; or forming the first dielectric material to have a first vertical thickness; and forming the second dielectric material to have a second vertical thickness which is less than the first vertical thickness of the first dielectric material, as recited in claim 19. Claim 8 is objected to because of its dependence from claim 7.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US20050258475; US 7763953; US 20020115252; US 20120205648; and US20060001111.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 2/25/2026