DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the amendments filed on 08/03/2026.
Applicant’s amendments filed 08/03/2026 have been fully considered and reviewed by the examiner. The examiner notes the amendment of claims 1 and 10; and the addition of new claims 21 and 22.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-6, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2017/0243834 to Lai et al. (hereinafter Lai).
With respect to claim 1, Lai discloses an integrated device package (e.g., an electronic package) (Lai, Figs. 4-5, ¶0002, ¶0032-¶0034, ¶0061-¶0077) comprising:
a glass interposer (e.g., the substrate body 20 is a glass substrate having through holes 200 filled with conductive material) (Lai, Figs. 2A, 4, ¶0033-¶0034, ¶0061-¶0062) comprising a glass substrate and having one or more conductive vias (e.g., through holes 200 filled with conductive material) extending through the glass substrate (20) from a top side (2a) of the glass interposer to a bottom side (2b) of the glass interposer, the bottom side (2b) of the glass interposer comprising one or more contact pads (25) (Lai, Figs. 2A, 2C, 4, ¶0066);
an integrated device die (40, a semiconductor chip) (Lai, Figs. 2A, 4, ¶0064) mounted and electrically connected to the top side (2a) of the glass interposer (20); and
an encapsulating material (42) (Lai, Figs. 2A, 4, ¶0065) disposed over at least a side surface of the glass interposer (20), on a portion of a top side of the glass substrate (20), and over a side surface of the integrated device die (40) (note that the term “on”/“over” is considered as a broad term which does not require two elements to be in direct contact).
Regarding claim 4, Lai discloses the integrated device package of Claim 1. Further, Lai discloses the integrated device package, further comprising one or more passive electronic components (e.g., an electronic component 40 includes a passive component) (Lai, Figs. 2A, 4, ¶0064) mounted to the glass interposer (20).
Regarding claim 5, Lai discloses the integrated device package of Claim 1. Further, Lai discloses the integrated device package, further comprising one or more solder balls (43) (Lai, Figs. 2A, 4, ¶0067) connected to the one or more contact pads (25) on the bottom side (2b) of the glass interposer (20).
Regarding claim 6, Lai discloses the integrated device package of Claim 1. Further, Lai discloses the integrated device package, wherein the encapsulating material (42) (Lai, Figs. 2A, 4, ¶0065) is disposed over a top side of the integrated device die (40).
Regarding claim 9, Lai discloses the integrated device package of Claim 1. Further, Lai discloses the integrated device package, wherein the encapsulating material (42) comprises an organic molding compound (e.g., epoxy resin) (Lai, Figs. 2A, 4, ¶0065).
Claims 1-2, 4-6, and 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2024/0178207 to Ecton et al. (hereinafter Ecton).
With respect to claim 1, Ecton discloses an integrated device package (e.g., multi-chip package of Figs. 1A, 2A and 5, wherein Fig. 5 is an example of a package including an assembly of Fig. 2A or 1A) (Ecton, Figs. 1A, 2A, 5, ¶0018-¶0028, ¶0071-¶0106) comprising:
a glass interposer (e.g., 103 in Figs. 1A, 2A or 2257 in Fig. 5) (Ecton, Figs. 1A, 2A, 5, ¶0071-¶0072, ¶0088, ¶0098-¶0103) comprising a glass substrate (e.g., glass material of the interposer) and having one or more conductive vias (e.g., through-glass vias TGVs 110 including conductive material) (Ecton, Figs. 1A, 2A, 5, ¶0071-¶0072) extending through the glass substrate (e.g., 103) from a top side (170-2) of the glass interposer (103) to a bottom side (170-1) of the glass interposer (103), the bottom side (170-1) of the glass interposer comprising one or more contact pads (174/2261) (Ecton, Figs. 1A, 2A, 5, ¶0082, ¶0102);
an integrated device die (128/2256, IC die 128 or dies 2256) (Ecton, Figs. 1A, 2A, 5, ¶0080, ¶0103) mounted and electrically connected to the top side (170-2) of the glass interposer (103); and
an encapsulating material (e.g., mold 2268) (Ecton, Figs. 1A, 2A, 5, ¶0104) disposed over at least a side surface of the glass interposer (103/2257), on a portion of a top side (170-2) of the glass substrate (103/2257), and over a side surface of the integrated device die (128/2256).
Regarding claim 2, Ecton discloses the integrated device package of Claim 1. Further, Ecton discloses the integrated device package, wherein the glass interposer (103) comprises borosilicate glass (Ecton, Figs. 1A, 2A, 5, ¶0072).
Regarding claim 4, Ecton discloses the integrated device package of Claim 1. Further, Ecton discloses the integrated device package, further comprising one or more passive electronic components (e.g., passive devices disposed on either side of the interposer) (Ecton, Figs. 1A, 2A, 5, ¶0106) mounted to the glass interposer (2257).
Regarding claim 5, Ecton discloses the integrated device package of Claim 1. Further, Ecton discloses the integrated device package, further comprising one or more solder balls (190/2265) (Ecton, Figs. 1A, 2A, 5, ¶0083, ¶0102) connected to the one or more contact pads (174/2261) on the bottom side (170-1) of the glass interposer (103/2257).
Regarding claim 6, Ecton discloses the integrated device package of Claim 1. Further, Ecton discloses the integrated device package, wherein the encapsulating material (e.g., mold 2268) (Ecton, Figs. 1A, 2A, 5, ¶0104) is disposed over a top side of the integrated device die (2256).
Regarding claim 9, Ecton discloses the integrated device package of Claim 1. Further, Ecton discloses the integrated device package, wherein the encapsulating material (e.g., mold 2268) comprises an organic molding compound (e.g., epoxy mold) (Ecton, Figs. 1A, 2A, 5, ¶0104).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0178207 to Ecton in view of Yun et al. (US 2014/0268615, hereinafter Yun) and Oran et al. (US Patent No. 11,201,602, hereinafter Oran).
Regarding claim 3, Ecton discloses the integrated device package of Claim 1. Further, Ecton discloses the integrated device package, wherein the glass interposer (103/2257) comprises one or more passive devices (e.g., passive devices disposed on either side of the interposer) (Ecton, Figs. 1A, 2A, 5, ¶0106), but does not specifically disclose that one or more passive devices configured to serve as a first electrical filter, and wherein the integrated device die comprises circuitry configured to serve as a second electrical filter.
However, Yun teaches forming the integrated device package (Yun, Figs. 5A-5D, ¶0027-¶0028, ¶0043-¶0047) comprising low pass filter capacitors integrated with through glass interposer inductor to control power delivery and frequency scaling for integrated circuits having high-power and to improve speed performance, and to achieve fast response.
Further, Oran teaches forming a tunable filter (see the annotated Fig. 1A below) (Oran, Figs. 1A-1B, Col. 3, lines 1-67; Col. 2-1-60; Col. 12, lines 39-52) comprising a semiconductor die (1) including controllable capacitors (e.g., 5a-5n) (Oran, Figs. 1A-1B, Col. 4 lines 36-60) on and the substrate (2/3) and connected to the inductors (e.g., 6a-6n) formed in the carrier circuit board/substrate (3), wherein tunable filters are controlled by changing a capacitance and an inductance of the integrated passive devices; specifically, the tunable filter is configured as a combination of low-pass filter and high-pass filter to filter set of frequencies based on input control signal for various RF applications.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the integrated device package of Ecton by forming low-pass filter capacitors integrated with through glass interposer inductors as taught by Yun, wherein the capacitor formed on the interposer and the inductors embedded into the interposer, and wherein tunable filter including controllable capacitors and inductors is configured as a combination of low-pass filter and high-pass filter as taught by Oran to have one or more passive devices configured to serve as a first electrical filter, and wherein the integrated device die comprises circuitry configured to serve as a second electrical filter, in order to provide integrated circuits including passive devices to have improved speed performance and to achieve fast response; and to provide tunable filters to filter set of frequencies based on input control signal for various RF applications (Yun, ¶0027-¶0028, ¶0043; Oran, Col. 3, lines 1-9; Col. 12, lines 46-52).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0178207 to Ecton in view of Yoo et al. (US 2022/0320043, hereinafter Yoo).
Regarding claims 7 and 8, Ecton discloses the integrated device package of Claim 1. Further, Ecton does not specifically disclose that a top side of the integrated device die is exposed through the encapsulating material (as claimed in claim 7); further comprising a heat slug disposed on the exposed top side of the integrated device die and on an upper surface of the encapsulating material (as claimed in claim 8).
However, Yoo teaches forming a semiconductor package (Yoo, Fig. 8, ¶0004-¶0005, ¶0043, ¶0024-¶0060), wherein a top side of the integrated device die (310) (Yoo, Fig. 8, ¶0058) is exposed through the encapsulating material (e.g., molding layer 410), and further comprising a heat slug (500) disposed on the exposed top side of the integrated device die (310) and on an upper surface of the encapsulating material (410), to provide a semiconductor package with improved electrical and thermal dissipation characteristics.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the integrated device package of Ecton by forming thermal radiation plate including high thermal conductivity material as taught by Yoo to have the integrated device package, wherein a top side of the integrated device die is exposed through the encapsulating material (as claimed in claim 7); further comprising a heat slug disposed on the exposed top side of the integrated device die and on an upper surface of the encapsulating material (as claimed in claim 8), in order to provide a semiconductor package with improved electrical and thermal dissipation characteristics (Yoo, ¶0004-¶0005, ¶0059).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0050334 to Pan et al. (hereinafter Pan) in view of Oran (US Patent No. 11,201,602).
With respect to claim 10, Pan discloses an integrated device package (e.g., integrated circuit comprising passive components embedded into a packaging substrate) (Pan, Fig. 7A, ¶0010-¶0013, ¶0033-¶0034, ¶0041, ¶0044-¶0045, ¶0050-¶0051) comprising:
an interposer (e.g., a packaging substrate 620) (Pan, Fig. 7A, ¶0044-¶0045) having one or more conductive vias (e.g., a through-via connected to the electrical path 624 to provide a voltage to the die 640) extending through the interposer (620) from one or more contact pads (642) (Pan, Fig. 7A, ¶0041) at a top side of the interposer (620) to one or more contact pads (622) at a bottom side of the interposer (620), the interposer (620) comprising one or more passive devices (e.g., vias 726 through interposer 620 having an inductance that acts as a filter and embedded capacitor 660) (Pan, Fig. 7A, ¶0044-¶0045) separate from the one or more conductive vias (e.g., a through-via connected to the electrical path 624 to provide a voltage to the die 640), wherein the one or more passive devices (e.g., vias 726 having an inductance that acts as a filter) are configured to serve as a first electrical filter (e.g., a filter for voltage provided from an active portion of the voltage regulator 640; and
an integrated device die (e.g., 640) (Pan, Fig. 7A, ¶0044-¶0045) mounted and electrically connected to the top side of the interposer (620), the integrated device die (142 or 502/542) comprising circuitry.
Further, Pan does not specifically disclose that the integrated device die comprising circuitry configured to serve as a second electrical filter.
However, Oran teaches forming a tunable filter (see the annotated Fig. 1A below) (Oran, Figs. 1A-1B, Col. 3, lines 1-67; Col. 2-1-60; Col. 12, lines 39-52) comprising a semiconductor die (1) including controllable capacitors (e.g., 5a-5n) (Oran, Figs. 1A-1B, Col. 4 lines 36-60) on the substrate (2/3) and connected to the inductors (e.g., 6a-6n) formed in the carrier circuit board/substrate (3), wherein tunable filters are controlled by changing a capacitance and an inductance of the integrated passive devices; specifically, the tunable filter is configured as a combination of low-pass filter and high-pass filter to filter set of frequencies based on input control signal for various RF applications.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the integrated device package of Pan forming a tunable filter including controllable capacitors and inductors configured as a combination of low-pass filter and high-pass filter as taught by Oran, wherein the low-pass filter capacitor formed on the interposer is configured as a second electrical filter, and the through interposer inductor of Pan is configured as a first electrical filter to have the integrated device package comprising: the integrated device die comprising circuitry configured to serve as a second electrical filter, in order to provide tunable filters to filter set of frequencies based on input control signal for various RF applications (Oran, Col. 3, lines 1-9; Col. 12, lines 46-52).
Claims 11 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0050334 to Pan in view of Oran (US Patent No. 11,201,602) as applied to claim 10, and further in view of Shin et al. (US 2024/0014160, hereinafter Shin).
Regarding claims 11 and 16, Pan in view of Oran discloses the integrated device package of Claim 10. Further, Pan does not specifically disclose an encapsulating material, wherein the interposer and the integrated device die are at least partially embedded in the encapsulating material (as claimed in claim 11); wherein the encapsulating material comprises an organic molding compound (as claimed in claim 16).
However, Shin teaches forming a semiconductor package (Shin, Fig. 7, ¶0003, ¶0005, ¶0028, ¶0056-¶0058) including high-speed and high-function electronic components with improved reliability, wherein the semiconductor package includes molding material (e.g., epoxy molding compound 500) (Shin, Fig. 7, ¶0056-¶0058) to surround the interposer (200) and the semiconductor die (300), wherein the encapsulating material (500) comprises an organic molding compound (e.g., epoxy molding compound (EMC)) (Shin, Fig. 7, ¶0046, ¶0058).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the integrated device package of Pan/Oran by forming molding material surrounding the interposer and the semiconductor die as taught by Shin to have the integrated device package, further comprising an encapsulating material, wherein the interposer and the integrated device die are at least partially embedded in the encapsulating material (as claimed in claim 11); wherein the encapsulating material comprises an organic molding compound (as claimed in claim 16), in order to provide improved semiconductor package including high-speed and high-function electronic components with improved reliability (Shin, ¶0003, ¶0005, ¶0046, ¶0056-¶0058).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0050334 to Pan in view of Oran (US Patent No. 11,201,602) as applied to claim 10, and further in view of Abe et al. (US 2019/0281697, hereinafter Abe).
Regarding claim 12, Pan in view of Oran discloses the integrated device package of Claim 10. Further, Pan does not specifically disclose that the interposer is composed of a material having a loss tangent of less than 0.02 at 10 GHz.
However, Abe discloses a semiconductor package (Abe, Figs. 1-2, ¶0001, ¶0013, ¶0155-¶0156, ¶0162-¶0172) comprising an interposer (e.g., wiring layer laminate 10) between the semiconductor chips (2A/2B) including RF chips (Abe, Figs. 1-2, ¶0164) and the substrate (11), wherein the interposer (e.g., wiring layer laminate 10) is composed of a material (e.g., resin compound) has a loss tangent (Abe, Figs. 1-2, ¶0156) of less than 0.02 (e.g., 0.012 or less) at 10 GHz, and the dielectric constant (Abe, Figs. 1-2, ¶0155) at 10 GHz less than 3.0, to suppress crosstalk between the wiring layers to improve the reliability of electric signals, and to provide wiring layers incorporated into the interposer with improved insulating reliability for high density interconnection between the chips.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the integrated device package of Pan/Oran by forming an interposer including wiring layer laminate as taught by Abe to have the integrated device package, wherein the interposer is composed of a material having a loss tangent of less than 0.02 at 10 GHz, in order to suppress crosstalk between the wiring layers to improve the reliability of electric signals, and to provide wiring layers incorporated into the interposer with improved insulating reliability for high density interconnection between the chips (Abe, ¶0001, ¶0013, ¶0155-¶0156).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0050334 to Pan in view of Oran (US Patent No. 11,201,602) and Abe (US 2019/0281697) as applied to claim 12, and further in view of Yun (US 2014/0268615).
Regarding claim 13, Pan in view of Oran and Abe discloses the integrated device package of Claim 12. Further, Pan does not specifically disclose that the interposer is composed of a glass material.
However, Pan teaches that through silicon vias are not necessarily constructed in silicon material, rather, the material can be any device substrate material (Pan, ¶0051). Further, Yun teaches forming the integrated device package, wherein the interposer (148/548) (Yun, Figs. 5A-5D, ¶0027-¶0028, ¶0037, ¶0044) includes a packaging substrate composed of a glass material to provide high density inductors using through glass vias and through glass interposer technology to achieve high-power and low-loss with improved impedance and performance (Yun, ¶0027).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the integrated device package of Pan/Oran/Abe by forming a packaging substrate as an interposer composed of a glass material as taught by Yun to have the integrated device package, wherein the interposer is composed of a glass material, in order to provide high density inductors using through glass vias and through glass interposer technology to achieve high-power and low-loss with improved impedance and performance (Yun, ¶0027).
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0050334 to Pan in view of Oran (US Patent No. 11,201,602) and Shin (US 2024/0014160) as applied to claim 11, and further in view of Yoo (US 2022/0320043).
Regarding claims 14 and 15, Pan in view of Oran and Shin discloses the integrated device package of Claim 11. Further, Pan does not specifically disclose that a top side of the integrated device die is exposed through the encapsulating material (as claimed in claim 14); further comprising a heat slug disposed on the exposed top side of the integrated device die and on an upper surface of the encapsulating material (as claimed in claim 15).
However, Yoo teaches forming a semiconductor package (Yoo, Fig. 8, ¶0004-¶0005, ¶0043, ¶0024-¶0060), wherein a top side of the integrated device die (310) (Yoo, Fig. 8, ¶0058) is exposed through the encapsulating material (e.g., molding layer 410), and further comprising a heat slug (500) disposed on the exposed top side of the integrated device die (310) and on an upper surface of the encapsulating material (410), to provide a semiconductor package with improved electrical and thermal dissipation characteristics.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the integrated device package of Pan/Oran/Shin by forming thermal radiation plate including high thermal conductivity material as taught by Yoo to have the integrated device package, wherein a top side of the integrated device die is exposed through the encapsulating material (as claimed in claim 14); further comprising a heat slug disposed on the exposed top side of the integrated device die and on an upper surface of the encapsulating material (as claimed in claim 15), in order to provide a semiconductor package with improved electrical and thermal dissipation characteristics (Yoo, ¶0004-¶0005, ¶0059).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0243834 to Lai in view of Garner et al. (US 2018/0166353, hereinafter Garner).
Regarding claim 21, Lai discloses the integrated device package of claim 1. Further, Lai does not specifically disclose that the integrated device die comprises one or more integrated device die operating frequencies in a range of 0.6 GHz to 250 GHz.
However, Garner teaches forming a glass substrate assembly (Garner, Fig. 1, ¶0005, ¶0022-¶0025) having desirable dielectric properties and dissipation loss values in response to electronic signals having frequency of 10GHz and higher, specifically for high-speed communication application with operating frequencies greater than 20GHz, 50GHz, or 100GHz.
The claimed range overlaps the ranges of Garner. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the integrated device package of Lai by forming the integrated device package including a glass substrate assembly as taught by Garner to have the integrated device package, wherein the integrated device die comprises one or more integrated device die operating frequencies in a range of 0.6 GHz to 250 GHz, in order to provide a package having desirable dissipation loss values in response to electronic signals for high-speed communication application (Garner, ¶0005, ¶0022-¶0025).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0178207 to Ecton in view of Garner (US 2018/0166353).
Regarding claim 21, Ecton discloses the integrated device package of claim 1. Further, Ecton does not specifically disclose that the integrated device die comprises one or more integrated device die operating frequencies in a range of 0.6 GHz to 250 GHz.
However, Garner teaches forming a glass substrate assembly (Garner, Fig. 1, ¶0005, ¶0022-¶0025) having desirable dielectric properties and dissipation loss values in response to electronic signals having frequency of 10GHz and higher, specifically for high-speed communication application with operating frequencies greater than 20GHz, 50GHz, or 100GHz.
The claimed range overlaps the ranges of Garner. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the integrated device package of Ecton by forming the integrated device package including a glass substrate assembly as taught by Garner to have the integrated device package, wherein the integrated device die comprises one or more integrated device die operating frequencies in a range of 0.6 GHz to 250 GHz, in order to provide a package having desirable dissipation loss values in response to electronic signals for high-speed communication application (Garner, ¶0005, ¶0022-¶0025).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0243834 to Lai in view of Abe (US 2019/0281697).
Regarding claim 22, Lai discloses the integrated device package of claim 1. Further, Lai does not specifically disclose that the glass interposer comprises a loss tangent of less than 0.02 at an integrated device die operating frequency of 10 GHz.
However, Abe discloses a semiconductor package (Abe, Figs. 1-2, ¶0001, ¶0013, ¶0155-¶0156, ¶0162-¶0172) comprising an interposer (e.g., wiring layer laminate 10) between the semiconductor chips (2A/2B) including RF chips (Abe, Figs. 1-2, ¶0164) and the substrate (11), wherein the interposer (e.g., wiring layer laminate 10) is composed of a material (e.g., resin compound) has a loss tangent (Abe, Figs. 1-2, ¶0156) of less than 0.02 (e.g., 0.012 or less) at 10 GHz, and the dielectric constant (Abe, Figs. 1-2, ¶0155) at 10 GHz less than 3.0, to suppress crosstalk between the wiring layers to improve the reliability of electric signals, and to provide wiring layers incorporated into the interposer with improved insulating reliability for high density interconnection between the chips.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the integrated device package of Lai by forming an interposer including wiring layer laminate as taught by Abe to have the integrated device package, wherein the glass interposer comprises a loss tangent of less than 0.02 at an integrated device die operating frequency of 10 GHz, in order to suppress crosstalk between the wiring layers to improve the reliability of electric signals, and to provide wiring layers incorporated into the interposer with improved insulating reliability for high density interconnection between the chips (Abe, ¶0001, ¶0013, ¶0155-¶0156).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0178207 to Ecton in view of Abe (US 2019/0281697).
Regarding claim 22, Ecton discloses the integrated device package of claim 1. Further, Ecton does not specifically disclose that the glass interposer comprises a loss tangent of less than 0.02 at an integrated device die operating frequency of 10 GHz.
However, Abe discloses a semiconductor package (Abe, Figs. 1-2, ¶0001, ¶0013, ¶0155-¶0156, ¶0162-¶0172) comprising an interposer (e.g., wiring layer laminate 10) between the semiconductor chips (2A/2B) including RF chips (Abe, Figs. 1-2, ¶0164) and the substrate (11), wherein the interposer (e.g., wiring layer laminate 10) is composed of a material (e.g., resin compound) has a loss tangent (Abe, Figs. 1-2, ¶0156) of less than 0.02 (e.g., 0.012 or less) at 10 GHz, and the dielectric constant (Abe, Figs. 1-2, ¶0155) at 10 GHz less than 3.0, to suppress crosstalk between the wiring layers to improve the reliability of electric signals, and to provide wiring layers incorporated into the interposer with improved insulating reliability for high density interconnection between the chips.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the integrated device package of Ecton by forming an interposer including wiring layer laminate as taught by Abe to have the integrated device package, wherein the glass interposer comprises a loss tangent of less than 0.02 at an integrated device die operating frequency of 10 GHz, in order to suppress crosstalk between the wiring layers to improve the reliability of electric signals, and to provide wiring layers incorporated into the interposer with improved insulating reliability for high density interconnection between the chips (Abe, ¶0001, ¶0013, ¶0155-¶0156).
Response to Arguments
Applicant's arguments filed 08/03/2026 have been fully considered but they are not persuasive.
In response to Applicant's argument that “Lai does not teach "an encapsulating material disposed ... on a portion of a top side of the glass substrate" and “[L]ai does not disclose or teach in a single Lai embodiment at least "an encapsulating material disposed over at least a side surface of the glass interposer, on a portion of a top side of the glass substrate, and over a side surface of the integrated device die" as recited in amended claim 1”, the examiner submits that the term “on”/“over” is considered as a broad term which does not require two elements to be in direct contact. Thus, Fig. 4 of Lai shows that an encapsulating material (42) is disposed over at least a side surface of the glass interposer (20), on a portion of a top side of the glass substrate, and over a side surface of the integrated device die (40), as required by claim 1.
Thus, the above Applicant's argument is not persuasive, and the rejection of claim 1 under 35 USC 102 to Lai is maintained.
In response to Applicant's argument that “Ecton teaches the encapsulating material and refers to the embodiment of FIG. 5. …However, FIG. 5 illustrates a different embodiment having an interposer 2257. Regarding interposer 2257, Ecton is silent regarding the interposer material, and similarly, is silent regarding the inclusion of "one or more conductive vias extending through the glass substrate” and “Ecton does not actually disclose or teach in a single Ecton embodiment, the combination of features recited in amended Claim 1 (e.g., "a glass interposer comprising a glass substrate and having one or more conductive vias …" and "an encapsulating material disposed over at least a side surface of the glass interposer, on a portion of a top side of the glass substrate, and over a side surface of the integrated device die")”, the examiner submits that Ecton teaches that Fig. 5 is an example of a package including an assembly of any of the embodiments (Ecton, Figs. 1A, 2A, 5, ¶0098-¶0099) disclosed by Ecton, and that includes an assembly of Fig. 2A or 1A. Thus, the package of Fig. 5 comprises the interposer (2257) configured as in the embodiment of Fig. 2A, wherein the interposer (103) includes "one or more conductive vias extending through the glass substrate”. Thus, the above Applicant's argument is not persuasive, and the rejection of claim 1 under 35 USC 102 to Ecton is maintained.
Regarding dependent claims 2-9, 11-16, and 21-22 which depend on the independent claims 1 and 10, the examiner respectfully submits that the applicant’s arguments with respect to dependent claims are not persuasive for the above reasons, thus, the rejections of the dependent claims are sustained.
Conclusion
Applicant's amendment of claim 10 necessitated the new ground of rejection of claim 10 presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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