DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election of Group I (claims (1-20, 22 and 23) in the reply filed on 04/06/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 21 and 24 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/06/2026.
Foreign Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file, as electronically retrieved 02/13/2024.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first specific layer must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
2. a. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 1, refers to a first specific layer but it is unclear based on para [0230-0280] which layer this first specific layer is pertaining to. Is the first specific layer a layer within a layer? Is it the first extension diffusion layer? the first pocket diffusion layer? the source/drain?
b. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is ambiguous. Claim 1, refers to a first specific layer but it is unclear based on para [0262-0280] which layer this first specific layer is pertaining to. Is the first specific layer a layer within a layer(s)? Is it the first extension diffusion layer? the first pocket diffusion layer? the source/drain? For the purpose of expediting prosecution, the Office is going to interpret the first specific layer as referring to the first pocket diffusion layer
Note: all dependent claims necessarily inherit the indefiniteness of the claims from which they depend.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/16/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-9, 11, 13-14, 19-20 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (PG Pub 2021/0074768; hereinafter Sato) and Noda (PG Pub 2009/0278209).
PNG
media_image1.png
500
664
media_image1.png
Greyscale
Regarding claim 1, refer to the Examiner’s mark-up of Fig. 3 provided above, Sato teaches an imaging device (see claim limitations below) comprising:
a pixel region R1 including a pixel substrate portion 130 (pix sub) and a pixel transistor 26 positioned in the pixel substrate portion (see Fig. 3); and
a first peripheral region R2 that includes a first peripheral substrate portion 130 (periph sub) and at least one first peripheral transistor 27 positioned in the first peripheral substrate portion (see Fig. 3), and that communicates a signal with the pixel region (see Fig. 3).
Sato does not teach the specific details of a transistor, such that the at least one (first peripheral) transistor includes a first specific layer positioned in the first peripheral substrate portion, and the first specific layer contains a heavy conductive impurity that is a p-type impurity having an atomic number greater than or equal to an atomic number of gallium or that is an n-type impurity having an atomic number greater than or equal to an atomic number of arsenic.
PNG
media_image2.png
294
492
media_image2.png
Greyscale
In the same field of endeavor, refer to Fig. 1 provided above, Noda teaches a transistor comprising: at least one transistor (n-MIS); wherein the at least one transistor includes a first specific layer 106/107, and the first specific layer contains a heavy conductive impurity that is a p-type impurity having an atomic number greater than or equal to an atomic number of gallium or that is an n-type impurity having an atomic number greater than or equal to an atomic number of arsenic (indium; para [0126-0132[).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the peripheral transistor for that of Noda, to “achieve an extension diffusion layer having a shallower junction and a lower resistance that is required for further miniaturization, and are useful for a MIS semiconductor device having high drive capability and a method of fabrication thereof, and the like” (para [0150]).
Regarding claim 2, refer to the figures cited above, Sato and Noda teach a concentration profile of the heavy conductive impurity (indium) in a region along a straight line extending in a depth direction of the first peripheral substrate 130-Sato portion through the first specific layer 106/107-Nado has a peak at a position deeper than an upper surface of the first peripheral substrate portion (inherent property of Indium, see Applicant’s Spec; para [0132]).
Regarding claim 3, refer to the figures cited above, Sato and Noda teach the first peripheral substrate portion 130-Sato includes a support substrate 140-Sato and a film body (portion of 130 above 140) positioned above the support substrate (see Fig. 3), the film body includes the first specific layer 107a/b and a low-concentration layer 106a/b that is positioned above the first specific layer, that has an upper surface of the film body, and that has a conductive impurity concentration lower than a conductive impurity concentration of the support substrate, and the at least one first peripheral transistor 27 includes the low-concentration layer and the first specific layer in sequence from top to bottom (see Fig. 1-Nado).
Regarding claim 4, refer to the figures cited above, Sato and Noda teach the heavy conductive impurity includes at least one selected from the group consisting of gallium, indium, antimony, and bismuth (para [0128]-Nado).
Regarding claim 5, refer to the figures cited above, Sato and Noda teach the at least one first peripheral transistor 27 and the pixel transistor 26 each include a gate 102-Nado, and a gate length of the at least one first peripheral transistor is equal to a gate length of the pixel transistor (see Fig. 3). Sato does not explicitly teach “a gate length of the at least one first peripheral transistor is shorter than a gate length of the pixel transistor.” However, one of ordinary skill in the art would have found it obvious to change the size of the gate length of the at least one first peripheral transistor (ex. to be shorter than, equal to or greater than) a gate length of the pixel transistor to better fit in the intended overall package.
Furthermore, according to MPEP § 2144(IV), where the facts in a prior legal decision are sufficiently similar to those in an application under examination, the examiner may use the rationale used by the court. Examples directed to various common practices which the court has held normally require only ordinary skill in the art and hence are considered routine expedients are discussed below.” See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). See Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree “will not sustain a patent”); and In re Williams, 36 F.2d 436, 438 (CCPA 1929) (“It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.”).
Regarding claim 6, refer to the figures cited above, Sato and Noda teach the pixel transistor 26-Sato includes a pixel gate insulating film 101-Nado, the at least one first peripheral transistor 27 includes a first peripheral gate insulating film 101-Nato, and the first peripheral gate insulating film is thinner than the pixel gate insulating film.
Sato and Nado do not explicitly teach “the first peripheral gate insulating film is thinner than the pixel gate insulating film.” However, one of ordinary skill in the art would have found it obvious to change the size of the first peripheral gate insulating film (ex. to be thinner than, equal to or thicker than) the pixel gate insulating film.
Furthermore, according to MPEP § 2144(IV), where the facts in a prior legal decision are sufficiently similar to those in an application under examination, the examiner may use the rationale used by the court. Examples directed to various common practices which the court has held normally require only ordinary skill in the art and hence are considered routine expedients are discussed below.” See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). See Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree “will not sustain a patent”); and In re Williams, 36 F.2d 436, 438 (CCPA 1929) (“It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.”).
Regarding claim 7, refer to the figures cited above, Sato and Noda teach the at least one first peripheral transistor 27-Sato includes a gate 102-Nado, a channel region 103-Nado positioned below the gate (see Fig. 1), a first source 113-L, a first drain 113-R, a first extension diffusion layer 106, and a first pocket diffusion layer 107, the first extension diffusion layer is adjacent to the first source or the first drain and is shallower than the first source and the first drain (see Fig. 1), the first pocket diffusion layer is adjacent to the first source or the first drain, and at least one selected from the group consisting of the channel region, the first extension diffusion layer, the first pocket diffusion layer, the first source, and the first drain includes the first specific layer (see claim 1).
Regarding claim 8, refer to the figures cited above, Sato and Noda teach the first specific layer 106/107-Nado contains at least one selected from the group consisting of carbon, nitrogen, and fluorine (para [0044-0045]).
Regarding claim 9, refer to the figures cited above, Sato and Noda teach the first specific layer 106/107-Nado contains at least one selected from the group consisting of germanium, silicon, and argon (para [0044-0045]).
Regarding claim 11, refer to the figures cited above, Sato and Noda teach the first specific layer 106/107 includes an end-of-range defect (para [0065]).
Regarding claim 13, refer to the figures cited above, Sato and Noda teach the at least one first peripheral transistor includes two first peripheral transistors 25 and 27, the first peripheral region includes a shallow trench isolation structure 220, the shallow trench isolation structure isolates the two first peripheral transistors (see Fig. 3), the shallow trench isolation structure has a trench, and a range in which the heavy conductive impurity is distributed in the first specific layer of at least one of the two first peripheral transistors is a range shallower than a bottom of the trench (see Fig. 3).
Regarding claim 14, refer to the figures cited above, Sato and Noda teach the pixel transistor 26-Sato includes a gate 102-Nado, a channel region 103-Nado positioned below the gate (see Fig. 1), and a pixel specific layer 103 that is positioned in the pixel substrate portion 130 (pix sub) and that contains the heavy conductive impurity, and the channel region includes the pixel specific layer (see Fig. 1).
Regarding claim 19, refer to the figures cited above, Sato and Noda teach the first peripheral region R2 is positioned outside the pixel region R1 (see Fig. 3), the pixel substrate portion 130 (pix sub) and the first peripheral substrate portion 130 (periph sub) are included in a single semiconductor substrate 130, the at least one first peripheral transistor 27 is a load transistor (see Fig. 3), and the pixel region is connected to the load transistor through a vertical signal line 39 (see Fig. 3).
Regarding claim 20, refer to the figures cited above, Sato and Noda teach the pixel substrate portion 130 (pix sub) and the first peripheral substrate portion 130 (periph sub) are stacked on each other (see Fig. 3).
Regarding claim 22, refer to the Examiner’s mark-up of Fig. 3 provided above, Sato teaches an imaging device (see claim limitations below) comprising:
a support substrate 140;
a film body 130 positioned above the support substrate (see Fig. 3); and
a pixel transistor 26, wherein the film body includes a low-concentration layer 62 including an upper surface of the film body and having a conductive impurity concentration lower than a conductive impurity concentration of the support substrate, and a conductive impurity layer that is positioned below the low-concentration layer and that contains a conductive impurity (extension regions abutting S/D), the pixel transistor includes the low-concentration layer and the conductive impurity layer in sequence from top to bottom (see Fig. 3).
Sato does not teach “a concentration profile of the conductive impurity in a region along a straight line extending in a depth direction of the film body through the low-concentration layer and the conductive impurity layer has a peak at a position deeper than the upper surface of the film body.”
In the same field of endeavor, refer to Fig. 1 provided above, Noda teaches a transistor comprising: a concentration profile of a conductive impurity in a region 107 along a straight line extending in a depth direction of a film body through a low-concentration layer 106 and the conductive impurity layer has a peak at a position deeper than the upper surface of the film body (as a result of the inclusion of Indium).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the peripheral transistor for that of Noda, to “achieve an extension diffusion layer having a shallower junction and a lower resistance that is required for further miniaturization, and are useful for a MIS semiconductor device having high drive capability and a method of fabrication thereof, and the like” (para [0150]).
Regarding claim 23, refer to the figures cited above, Sato and Noda teach the conductive impurity layer contains a heavy conductive impurity that is a p-type impurity an atomic number of which is equal to or greater than an atomic number of gallium (para [0071])or that is an n-type impurity an atomic number of which is equal to or greater than an atomic number of arsenic (para [0128]).
Allowable Subject Matter
5. Claims 10, 12, and 15-18 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 10 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 10, the pixel region includes a charge storage region being an impurity region that stores a charge generated by photoelectric conversion, the pixel transistor includes a gate and a channel region positioned below the gate, and a concentration of carbon in the first specific layer is higher than a concentration of carbon in the charge storage region or a concentration of carbon in the channel region.
Claim 12 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 12, the first specific layer includes a first segregation portion in which the heavy conductive impurity is segregated in a depth direction of the first peripheral substrate portion, the pixel region includes a charge storage region being an impurity region that stores a charge generated by photoelectric conversion, and the first segregation portion is shallower than the charge storage region.
Claim 15 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 15, a second peripheral region including a second peripheral substrate portion and a second peripheral transistor positioned in the second peripheral substrate portion, wherein the signal is communicated between the first peripheral region and the pixel region through the second peripheral region, the at least one first peripheral transistor includes a first source, a first drain, and a first extension diffusion layer, the first extension diffusion layer is adjacent to the first source or the first drain and is shallower than the first source and the first drain, the second peripheral transistor includes a second source, a second drain, and a second extension diffusion layer, the second extension diffusion layer is adjacent to the second source or the second drain and is shallower than the second source and the second drain, a concentration of a conductive impurity in the second extension diffusion layer is lower than a concentration of a conductive impurity in the first extension diffusion layer, the second extension diffusion layer is deeper than the first extension diffusion layer, the at least one first peripheral transistor, the second peripheral transistor, and the pixel transistor each include a gate, a gate length of the at least one first peripheral transistor is shorter than a gate length of the second peripheral transistor, and a gate length of the pixel transistor is longer than the gate length of the second peripheral transistor. Claims 16-18 would be allowable, because they depend on allowable claim 15.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTINA A SYLVIA/Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Prosecution Insights