DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites: The memory according to claim 1, wherein the surface in the first electrode facing the second electrode is the first wall surface, and the surface in the first electrode adjacent to the first wall surface is the first side surface, the surface in the second electrode facing the first electrode is the second wall surface, the surface is in the second electrode adjacent to the second wall surface is the second side surface, and the first side surface and the second side surface are located on a same side, and the gate is located on a side close to the first side surface and the second side surface.
This is indefinite because it is unclear as to what location on the transistor is distinctly being claimed as a location for the gate on the transistor
For the purpose of examination on the merits, Claim 9 has been interpreted to recite the memory according to claim 1, wherein the surface in the first electrode facing the second electrode is the first wall surface, and the surface in the first electrode adjacent to the first wall surface is the first side surface, the surface in the second electrode facing the first electrode is the second wall surface, the surface is in the second electrode adjacent to the second wall surface is the second side surface, and the first side surface and the second side surface are located on a same side, and the gate is located between the first wall surface and the second wall surface.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8, 9, 10, 13, 15, 16, 19 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sharma(US20200098931A1).
With respect to Claim 1, Fig 4(f) and Fig 6 disclose, a memory comprising:
a substrate (Fig 4(f); 401; ¶ [0056]); and
a plurality of storage units formed on the substrate (Fig 6; 602; 604; 606; 608; ¶ [0073]), wherein each of the storage units comprises:
a capacitor (Fig 6; 612; ¶ [0073]); and
a transistor electrically connected to the capacitor (Fig 6; 614; ¶ [0071]), wherein the transistor and the capacitor are arranged in a first direction perpendicular to the substrate (Fig 6; 612 and 614; both transistor and capacitor have a side faced in the vertical direction (arranged in a first direction) on substrate surface (perpendicular)), wherein the transistor comprises:
a gate dielectric layer (Fig 4(f); 407; ¶ [0059]);
a first electrode (Fig 4(f); 421; ¶ [0056]);
a second electrode (Fig 4(f); 423; ¶ [0057]), wherein the first electrode and the second electrode are arranged in the first direction (Fig 4(f); 421 and 423; the first electrode and second electrode have a side faced in the vertical direction (arranged in the first direction));
a gate, located between the first electrode and the second electrode (Fig 4(f); 405; ¶ [0063]); and
a semiconductor layer located on one of two opposite sides of the gate in the second direction (Fig 4(f); 409; ¶ [0063]), wherein the semiconductor layer is electrically connected separately to the first electrode (Fig 4(f); 425; ¶ [0056]; via connecting 409 and 421) and the second electrode (Fig 4(f); 427; ¶ [0063]; via connecting 409 and 421), wherein the gate and the semiconductor layer are isolated from each other by the gate dielectric layer (Fig 4(f); 407; ¶ [0059]), and wherein the second direction is a direction parallel to the substrate.
With respect to Claim 8, Fig 4(f) discloses, the memory according to claim 1, wherein the surface in the first electrode facing the second electrode is the first wall surface (Figure 4(f) with annotations; first wall surface; 421; ¶ [0056]), the surface in the second electrode facing the first electrode is the second wall surface (Figure 4(f) with annotations; second wall surface; 423; ¶ [0057]), and the gate is located in a region between the first wall surface and the second wall surface (Figure 4(f) with annotations; 405; ¶ [0060]).
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With respect to Claim 9, Fig 4(f) discloses, the memory according to claim 1, wherein the surface in the first electrode facing the second electrode is the first wall surface (Figure 4(f) with annotations; first wall surface; 421; ¶ [0056]), and the surface in the first electrode adjacent to the first wall surface is the first side surface (Figure 4(f) with annotations; first side surface; 421; ¶ [0056]), the surface in the second electrode facing the first electrode is the second wall surface (Figure 4(f) with annotations; second wall surface; 423; ¶ [0057]), the surface is in the second electrode adjacent to the second wall surface is the second side surface (Figure 4(f) with annotations; second side surface; 423; ¶ [0057]), and the first side surface and the second side surface are located on a same side (Figure 4(f) with annotations; first side surface and second side surface), and the gate is located between the first wall surface and the second wall surface (Figure 4(f) with annotations; 405; ¶ [0060]).
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With respect to Claim 10, ¶ [0012] discloses, the memory according to claim 1, wherein both the transistor and the capacitor are manufactured by using a back end of line process (¶ [0012]; BEOL; individual devices are interconnected with wiring on the wafer which is part of the manufacturing process).
With respect to Claim 13, Fig 6 discloses, the memory according to claim 1, wherein the memory further comprises bit lines (Fig 6; B1 and B2; ¶ [0072]) and word lines (Fig 6; W1 and W2; ¶ [0072]), wherein the gate is electrically connected to the word lines (Fig 6; ¶ [0071]; gate electrode coupled to word line), and the second electrode is electrically connected to the bit lines (Fig 6; ¶ [0017]; First electrode coupled to bit line and second electrode coupled to first electrode so second electrode is electrically connected to bit line).
With respect to Claim 15, ¶ [0082] discloses the memory according to claim 13, wherein the memory further comprises a controller (¶ [0082]; voltage regulator (not shown)) configured to:
output a word line control signal to control a voltage on each of the word lines (¶ [0082]; voltage regulator (not shown)); and
output a bit line control signal to control a voltage on each of the bit lines (¶ [0082]; voltage regulator (not shown)).
With respect to Claim 16, Fig 4(f), Fig 6 and Fig 8 disclose, an electronic device comprising:
a processor (Fig 8; 804; ¶ [0080]); and
a memory (Fig 8; 806; ¶ [0080]) electrically connected to the processor, wherein the memory comprises:
a substrate (Fig 4(f); 401; ¶ [0056]); and
a plurality of storage units formed on the substrate (Fig 6; 602; 604; 606; 608; ¶ [0073]), wherein each of the storage units comprises:
a capacitor (Fig 6; 612; ¶ [0073]); and
a transistor electrically connected to the capacitor (Fig 6; 614; ¶ [0071]), wherein the transistor and the capacitor are arranged in a first direction perpendicular to the substrate (Fig 6; 612 and 614; both transistor and capacitor have a side faced in the vertical direction (arranged in a first direction) on the substrate surface (perpendicular)), wherein the transistor comprises:
a gate dielectric layer (Fig 4(f); 407; ¶ [0059]);
a first electrode (Fig 4(f); 421; ¶ [0056]);
a second electrode (Fig 4(f); 423; ¶ [0057]), wherein the first electrode and the second electrode are arranged in the first direction (Fig 4(f); 421 and 423; the first electrode and second electrode have a side faced in the vertical direction (arranged in the first direction));
a gate, located between the first electrode and the second electrode (Fig 4(f); 405; ¶ [0063]); and
a semiconductor layer located on one of two opposite sides of the gate in the second direction (Fig 4(f); 409; ¶ [0063]), wherein the semiconductor layer is electrically connected separately to the first electrode (Fig 4(f); 425; ¶ [0056]; via connecting 409 and 421) and the second electrode (Fig 4(f); 527; ¶ [0063]; via connecting 409 and 421), wherein the gate and the semiconductor layer are isolated from each other by the gate dielectric layer (Fig 4(f); 407; ¶ [0059]), and wherein the second direction is a direction parallel to the substrate.
With respect to Claim 19, ¶ [0104] and Fig 6 disclose, a memory forming method comprising:
forming a first electrode (¶ [0104]; first metal electrode) and a second electrode (¶ [0104]; second metal electrode) in a first direction perpendicular to a substrate;
forming a semiconductor layer (¶ [0104]; channel layer), a gate (¶ [0104]; gate electrode), and a gate dielectric layer (¶ [0104]; first dielectric layer), wherein the semiconductor layer (¶ [0104]; channel layer) is located on one of two opposite sides of the gate (¶ [0104]; gate electrode) in a second direction, the semiconductor layer is electrically connected separately to the first electrode (¶ [0104]; channel layer is coupled to the fist short via) and the second electrode (¶ [0104]; second short via coupled to a second portion of the channel layer), and the gate dielectric layer is formed between the gate and the semiconductor layer (¶ [0104]; forming a first dielectric layer including a gate dielectric material within an opening of the channel layer, wherein the first dielectric layer is oriented in the vertical direction, and adjacent to the channel layer; forming a gate electrode within an opening of the first dielectric layer, wherein the gate electrode is oriented in the vertical direction, and adjacent to the first dielectric layer), to form a transistor (¶ [0104]; a method for forming a vertical thin film transistor (TFT)), wherein the second direction is a direction parallel to the substrate; and
forming a capacitor (Fig 6; 612; ¶ [0073]), and making the capacitor electrically connected to the transistor (Fig 6; 614; ¶ [0073]) to form a storage unit (Fig 6; 602; ¶ [0073]).
With respect to Claim 20, Fig 8 discloses, the memory forming method according to claim 19, wherein before forming the storage unit, the method further comprises:
forming a control circuit on the substrate (Fig 8; ¶ [0104]; integrated circuit chip that may be bonded to the substrate); and
forming, on the control circuit, interconnects that electrically connect the control circuit and the storage (Fig 8; integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 802. The integrated circuit die 802 may include a processor 804 as well as on-die memory 806)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3, 7, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma(US2020098931A1) and Karda(US11139396B2).
With respect to Claim 2, Sharma teaches in Fig 4(f) the memory according to claim 1,
wherein the semiconductor layer has a vertical structure extending in the first direction (Fig 4(f); 409; ¶ [0058]).
Sharma does not teach a first end of two opposite ends of the semiconductor layer in the first direction is in contact with the first electrode, and a second end of the two opposite ends of the semiconductor layer is in contact with the second electrode.
Karda teaches in Fig 1A, a first end of two opposite ends of the semiconductor layer in the first direction is in contact with the first electrode (Fig 1A; 118 and 114; Col 7 Line 45-48 and Line 56-59), and a second end of the two opposite ends of the semiconductor layer is in contact with the second electrode (Fig 1A; 118 and 105; Col 7 Line 45-48 and 56-59).
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Sharma, a vertical thin film transistor device and the invention of Karda, a vertical transistor with a semiconductor with a vertical structure in contact with an upper electrode and a bottom electrode. This combination would produce a vertical transistor with a vertical structure in contact with an upper electrode and a bottom electrode. This configuration allows for electrical commination between the upper electrode and bottom electrode for responses to suitable voltages Karda(Col 8 Line 23-29).
With respect to Claim 3, Sharma teaches the memory according to claim 2.
Sharma teaches in Fig 4(f), wherein a surface in the first electrode facing the second electrode is a first wall surface (Fig 4(f) with annotations; First wall surface; 421; ¶ [0056]), and a surface in the second electrode facing the first electrode is a second wall surface (Fig 4(f) with annotations; Second wall surface; 423; ¶ [0057]), and
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Sharma does not teach the first end of the two opposite ends of the semiconductor layer in the first direction is in contact with the first wall surface, and the second end of the two opposite ends of the semiconductor layer is in contact with the second wall surface.
Karda teaches in Fig 1A, wherein a surface in the first electrode facing the second electrode is a first wall surface (Fig 1A with annotation; First wall surface), and a surface in the second electrode facing the first electrode is a second wall surface (Fig 1A with annotation; Second wall), and the first end of the two opposite ends of the semiconductor layer in the first direction is in contact with the first wall surface (Fig 1A with annotations; 118 and 105; Col 7 Line 45-48 and Line 56-59), and the second end of the two opposite ends of the semiconductor layer is in contact with the second wall surface (Fig 1A with annotations; 118 and 114; Col 7 Line 45-48 and Line 56-59).
It would be obvious to one with ordinary skill before the effective filing date of the invention to combine the invention of Sharma, a vertical thin film transistor device and the invention of Karda, a vertical transistor with a semiconductor with a vertical structure in contact with an upper electrode and a bottom electrode. This combination would produce a vertical transistor with a vertical structure in contact with the first wall surface and the second wall surface. This configuration allows for electrical commination between the upper electrode and bottom electrode for responses to suitable voltages Karda(Col 8 Line 23-29).
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With respect to Claim 7, Sharma teaches in Fig 4(f), the memory according to claim 1,
wherein the semiconductor layer comprises a first portion (Fig 4(f) with annotations; first portion) extending in the second direction and a third portion (Fig 4(f) with annotations; third portion) extending in the first direction and connected to the first portion (Fig 4(f) with annotations; first portion and third portion), wherein a surface in the first electrode facing the second electrode is a first wall surface (Fig 4(f) with annotations; first wall), and a surface in the second electrode facing the first electrode is a second wall surface (Fig 4(f) with annotations; second wall), wherein the memory further comprises a connection electrode (Fig 4(f); 427 and 425; ¶ [0063]) disposed on the second wall surface,
and the first portion is in contact with the connection electrode portion (Fig 4(f) with annotations; first portion).
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Sharma does not teach the third portion is in contact with the first wall surface.
Karda teaches in Fig 1A, the third portion is in contact with the first wall surface (Fig 1A with annotations; 218; Col 16 Line 37-39).
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It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Sharma, a vertical thin film transistor device and the invention of Karda, a vertical transistor with a semiconductor layer in contact with an upper electrode and a lower electrode. This combination would produce a vertical transistor with a first portion, a second portion and a third portion, with the third portion in contact with an upper electrode and a lower electrode. The semiconductor layer is configured to exhibit electrical conductivity responsive to application of a suitable voltage Karda(Col 8 Line 23-28). The direct contact of the semiconductor material allows for the upper and lower electrode to electrically communicate between one another.
With respect to Claim 17, Sharma teaches in Fig 4(f), the memory according to claim 16,
wherein the semiconductor layer has a vertical structure extending in the first direction (Fig 4(f); 409; ¶ [0058]).
Sharma does not teach a first end of two opposite ends of the semiconductor layer in the first direction is in contact with the first electrode, and a second end of the two opposite ends of the semiconductor layer is in contact with the second electrode.
Karda teaches in Fig 1A, a first end of two opposite ends of the semiconductor layer in the first direction is in contact with the first electrode (Fig 1A; 118 and 114; Col 7 Line 45-48 and Line 56-59), and a second end of the two opposite ends of the semiconductor layer is in contact with the second electrode (Fig 1A; 118 and 105; Col 7 Line 45-48 and 56-59).
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Sharma, a vertical thin film transistor device and the invention of Karda, a vertical transistor with a semiconductor with a vertical structure in contact with an upper electrode and a bottom electrode. This combination would produce a vertical transistor with a vertical structure in contact with an upper electrode and a bottom electrode. This configuration allows for electrical commination between the upper electrode and bottom electrode for responses to suitable voltages Karda(Col 8 Line 23-29).
With respect to Claim 18, Sharma teaches the memory according to claim 17.
Sharma does not teach wherein a surface in the first electrode facing the second electrode is a first wall surface, and a surface in the second electrode facing the first electrode is a second wall surface, and the first end of the two opposite ends of the semiconductor layer in the first direction is in contact with the first wall surface, and the second end of the two opposite ends of the semiconductor layer is in contact with the second wall surface.
Karda teaches in Fig 1A, wherein a surface in the first electrode facing the second electrode is a first wall surface (Fig 1A with annotation; First wall), and a surface in the second electrode facing the first electrode is a second wall surface (Fig 1A with annotation; Second wall), and the first end of the two opposite ends of the semiconductor layer in the first direction is in contact with the first wall surface (Fig 1A with annotations; 118 and 105; Col 7 Line 45-48 and Line 56-59), and the second end of the two opposite ends of the semiconductor layer is in contact with the second wall surface (Fig 1A with annotations; 118 and 114; Col 7 Line 45-48 and Line 56-59).
It would be obvious to one with ordinary skill before the effective filing date of the invention to combine the invention of Sharma, a vertical thin film transistor device and the invention of Karda, a vertical transistor with a semiconductor with a vertical structure in contact with an upper electrode and a bottom electrode. This combination would produce a vertical transistor with a vertical structure in contact with the first wall surface and the second wall surface. This configuration allows for electrical commination between the upper electrode and bottom electrode for responses to suitable voltages Karda(Col 8 Line 23-29).
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Claims 4, 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma(US20200098931A1) and Karda(US11139396B2) as applied to claim 2, 3, 7, 17 and 18 above, and further in view of Park(US20120018799A1).
With respect to Claim 4, Sharma and Karda teach the memory according to claim 2.
Sharma teaches in Fig 4(f), wherein a surface in the first electrode facing the second electrode is a first wall surface (Fig 4(f) with annotations; First wall surface; 421; ¶ [0056]), and a surface in the first electrode adjacent to the first wall surface is a first side surface (Fig 4(f) with annotations; First side surface; 421; ¶ [0056]), a surface in the second electrode facing the first electrode is a second wall surface (Fig 4(f) with annotations; Second wall surface; 423; ¶ [0064]),, a surface in the second electrode adjacent to the second wall surface is a second side surface (Fig 4(f) with annotations; Second side surface; 423; ¶ [0064]), and the first side surface and the second side surface are located on a same side surface (Fig 4(f) with annotations; First side surface and Second side surface).
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Sharma does not teach the first end of the two opposite ends of the semiconductor layer in the first direction is in contact with the first side surface, and the second end of the two opposite ends of the semiconductor layer is in contact with the second side surface.
Park teaches in Fig 3i, wherein a surface in the first electrode facing the second electrode is a first wall surface (Fig 3i with annotations; First wall, 230; ¶ [0051]) and a surface in the first electrode adjacent to the first wall surface is a first side surface (Fig 3i with annotations; First side surface, 230; ¶ [0051]), a surface in the second electrode facing the first electrode is a second wall surface (Fig 3i with annotations; Second wall, 230; ¶ [0051]), a surface in the second electrode adjacent to the second wall surface is a second side surface (Fig 3i with annotations; Second side surface, 230; ¶ [0051]), and the first side surface and the second side surface are located on a same side (Fig 3i with annotations; First side surface and Second side surface, 230; ¶ [0051]), the first end of the two opposite ends of the semiconductor layer in the first direction is in contact with the first side surface (Fig 3i with annotations; 225; ¶ [0049]), and the second end of the two opposite ends of the semiconductor layer is in contact with the second side surface (Fig 3i with annotations; 225; ¶ [0049]).
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It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the inventions of Sharma and Karda, a vertical thin film transistor device with a vertical semiconductor layer and the invention of Park, a semiconductor device with a semiconductor layer in contact with the first surface side of the first electrode and the second surface side of the second electrode. This combination in inventions would produce a vertical transistor with a vertical semiconductor layer with each opposite end in contact with the first surface side of the first electrode and the second surface side of the second electrode. The semiconductor device of Park turned sideways 90 degrees reads on the limitations presented in the claim. Depositing a semiconductor material over two electrodes serves as the channel region for the transistor Park(¶ [0050]).
With respect to Claim 5, Sharma teaches in Fig 4(f), the memory according to claim 1.
wherein the semiconductor layer comprises:
a first portion (Fig 4(f) with annotation; First portion), a second portion (Fig 4(f) with annotation; Second portion), wherein the first portion and the second portion both extend in the second direction (Fig 4(f) with annotation; First portion and Second portion); and
a third portion (Fig 4(f) with annotation; Third portion) extending in the first direction and connected to the first portion and the second portion;
wherein a surface in the first electrode facing the second electrode is a first wall surface (Fig 4(f) with annotation; First wall), a surface in the second electrode facing the first electrode is a second wall surface Fig 4(f) with annotation; Second wall),
Sharma does not teach the first portion is disposed on the first wall surface, and the second portion is disposed on the second wall surface.
Park teaches in Fig 3i, first portion is disposed on the first wall surface (Fig 3i; First wall surface; First portion; 225; ¶ [0053]), and the second portion is disposed on the second wall surface (Fig 3i; Second wall surface; Second portion; 225; ¶ [0053]).
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Sharma and Karda, a vertical thin film transistor device and the invention of Park, a semiconductor device with a semiconductor layer with a first potion in contact with the first wall and the second portion in contact with the second wall. This combination in inventions would produce a vertical transistor with a semiconductor layer with a first potion in contact with the first wall and the second portion in contact with the second wall. The semiconductor device of Park turned sideways 90 degrees reads on the limitations presented in the claim. Depositing a semiconductor material over the two electrodes serve as the channel region for the transistor Park(¶ [0050]).
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With respect to Claim 6, Sharma and Park teach the memory according to claim 5.
Sharma teaches in Fig 4(f), wherein the first portion (Fig 4(f) with annotations; first portion), the second portion (Fig 4(f) with annotations; second portion), and the third portion (Fig 4(f) with annotations; third portion) are connected to form an integral structure (Fig 4(f) with annotations; first portion, second portion and third portion).
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Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma(US2020098931A1) and Huang(CN101673744B).
With respect to Claim 11, Sharma teaches the memory according to claim 1.
Sharma does not teach wherein the capacitor comprises a first electrode layer, a second electrode layer, and a capacitor dielectric layer isolating the first electrode layer from the second electrode layer, and the first electrode layer of the capacitor is electrically connected to the first electrode in the transistor and close to the capacitor.
Huang teaches in Fig 1, wherein the capacitor comprises a first electrode layer (Fig 1; 46; ¶ [0039]), a second electrode layer (Fig 1; 50; ¶ [0039]), and a capacitor dielectric layer (Fig 1; 48; ¶ [0039]) isolating the first electrode layer from the second electrode layer, and the first electrode layer of the capacitor is electrically connected to the first electrode in the transistor and close to the capacitor (Fig 1; 46; ¶ [0039]; conductive material is connected to transistor compartment of device and in contact with top conductive plug 32 which would replace top electrode of Sharma’s transistor device).
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Sharma, a vertical thin film transistor device and the invention of Huang, a capacitor with two electrodes and a dielectric layer between the two. This combination in inventions would produce a vertical thin film transistor device and, a capacitor with two electrodes and a dielectric layer between the two. This capacitor structure is a well-known stacked structure and the method to make is well known Huang(¶ [0039]).
With respect to Claim 12, Sharma and Huang teach the memory according to claim 11.
Sharma does not teach wherein the first electrode layer extends in the first direction, and the second electrode layer surrounds a periphery of the first electrode layer.
Huang teaches in Fig 1, wherein the first electrode layer extends in the first direction (Fig 1; 46; ¶ [0039]), and the second electrode layer surrounds a periphery of the first electrode layer (Fig 1; 50; ¶ [0039]).
It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Sharma, a vertical thin film transistor device and the invention of Huang, a capacitor with two electrodes and a dielectric layer between the two. This combination in inventions would produce a vertical thin film transistor device and, a capacitor with two electrodes and a dielectric layer between the two. This capacitor structure is a well-known stacked structure and the method to make is well known Huang(¶ [0039]).
Claim 14 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma(US2020098931A1) and Guk(KR20000066848A).
With respect to Claim 14, Sharma teaches in Fig 5, the memory according to claim 13,
the second electrodes of the plurality of storage units arranged in the second direction are electrically connected to a same bit line (Fig 5 with annotations; 509 and B1; ¶ [0069]), and the gates of the plurality of storage units arranged in the third direction are electrically connected to a same word line (Fig 5 with annotations; 511 and W1; ¶ [0017]).
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Sharma does not teach wherein the bit lines all extend in the second direction, the word lines extend in a third direction, the second direction is perpendicular to the third direction
Guk teaches in Fig 1, wherein the bit lines all extend in the second direction (Fig 1 with annotations; bit line pairs 1a and 1b), the word lines extend in a third direction (Fig 1 with annotations; word lines 20 to 25), the second direction is perpendicular to the third direction (Fig 1 with annotations; bit line pairs 1a and 1b are arranged perpendicular to word lines 20 to 25),
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It would be obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Sharma, a vertical thin film transistor device and the invention of Guk, a set of bit lines and word lines arranged perpendicularly to one another. This combination would produce a vertical thin film transistor device with bit lines and word lines arranged perpendicularly to one another. The bit lines and word lines crossing perpendicularly allows for memory cells to be connected at an intercession point between bit lines and word lines Guk(¶ [02]), allowing for a high density of memory cells to be connected.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Kim(US20120156868A1); A method for fabricating a semiconductor device with a plurality of bodies.
Lin(US20130049085A1); A plurality of transitions with vertical channels formed on a semiconductor substrate
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/B.Q.R./Examiner, Art Unit 2817
/RATISHA MEHTA/ Primary Examiner, Art Unit 2817
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