DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 5/15/26 is acknowledged.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,484,430. Although the claims at issue are not identical, they are not patentably distinct from each other because they overlap in scope. Bold text reference the cited patent
Pertaining to claim 1:
A display panel comprising: A display panel, comprising (claim 1)
a substrate; an array substrate (claim 1)
a functional metal layer disposed on the substrate and comprising a capacitor plate, a light-shielding pattern, and a metal wiring disposed at intervals, wherein areas where the capacitor plate, the light-shielding pattern, and the metal wiring are located are defined as a capacitance area, a light-shielding area, and a metal wiring area, respectively; a buffer layer disposed on the functional metal layer, wherein a part of the buffer layer disposed in the capacitance area is provided with a first thinning structure; and a semiconductor layer disposed on the buffer layer and comprising a first semiconductor disposed corresponding to the capacitor plate; wherein the first semiconductor is disposed on the first thinning structure and capable of forming a first capacitance with the capacitor plate. wherein the array substrate comprises a light shielding layer, a first capacitor plate, a buffer layer, a semiconductor layer, a second capacitor plate, and a gate insulating layer, a gate layer, an interlayer insulating layer, a drain wiring, a source wiring, an auxiliary cathode wiring, a passivation layer, and a planarization layer which are sequentially stacked on a side of the substrate; and the pixel electrode layer and the electric field electrode layer are disposed on the planarization layer. (claim 1)
Note thinning structure = planarization layer
Allowable Subject Matter
Claims 2-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Pertaining to claim 2, the prior art fails to teach wherein the semiconductor layer further comprises a second semiconductor and a third semiconductor disposed corresponding to the light-shielding pattern and the metal wiring, respectively; the second semiconductor comprises a channel area and source/drain lap-jointed areas disposed at two sides of the channel area; and a part of the buffer layer disposed in the metal wiring area is provided with a first via hole, and the third semiconductor is in direct contact with the metal wiring through the first via hole
Pertaining to claim 7, the prior art fails to teach wherein the first thinning structure is a stepped groove having at least one step.
Pertaining to claim 9, the prior art fails to teach wherein a width of the first thinning structure is greater than or equal to a width of the capacitor plate.
Pertaining to claim 10, the prior art fails to teach the panel further comprising: an interlayer dielectric layer disposed on the semiconductor layer and comprising a second thinning structure disposed in the capacitance area; and a source/drain electrode layer disposed on the interlayer dielectric layer and comprising a source/drain capacitor plate disposed in the capacitance area; wherein the source/drain capacitor plate is disposed on the second thinning structure and capable of forming a second capacitance with the first semiconductor.
Claims 16-18 are allowed.
The following is an examiner’s statement of reasons for allowance: The primary reason for the allowance of the claims is the inclusion of the limitation a functional metal layer disposed on the substrate and comprising a capacitor plate, a light-shielding pattern, and a metal wiring disposed at intervals, wherein areas where the capacitor plate, the light-shielding pattern, and the metal wiring are located are defined as a capacitance area, a light-shielding area, and a metal wiring area, respectively; a buffer layer disposed on the functional metal layer, wherein a part of the buffer layer disposed in the capacitance area is provided with a first thinning structure; a semiconductor layer disposed on the buffer layer and comprising a first semiconductor disposed corresponding to the capacitor plate, wherein the first semiconductor is disposed on the first thinning structure and capable of forming a first capacitance with the capacitor plate; an interlayer dielectric layer disposed on the semiconductor layer and comprising a second thinning structure disposed in the capacitance area; and a source/drain electrode layer disposed on the interlayer dielectric layer and comprising a source/drain capacitor plate disposed in the capacitance area, wherein the source/drain capacitor plate is disposed on the second thinning structure and capable of forming a second capacitance with the first semiconductor; wherein both of the first thinning structure and the second thinning structure are stepped grooves, in all of the claims which is not found in the prior art references.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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