DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 6 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites “a projection area of the second hole on the array substrate” in lines 1-2 of the claim, however “a projection area of the second hole on the array substrate” element was already introduced earlier in lines 15-16 of claim 1, which claim 2 depends from, and thereby it is unclear whether the “a projection area of the second hole on the array substrate” in lines 1-2 of the claim is directed to that same element and therefore should be properly amended to “the projection area of the second hole on the array substrate” or directed to an entirely different element and therefore should be amended with specific language to distinguish it from the already introduced element.
Claim 6 recites the limitation “the capacitor area” in lines 1-2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 16 recites the limitation “the capacitor area” in lines 1-2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Heo et al. (US 2016/0043341 A1, hereinafter “Heo”).
Regarding independent claim 1, Figure 9F of Heo discloses a display panel, comprising:
an array substrate 920/934 (collectively 920 and 934), comprising a first electrode layer 920/934 (collectively 920 “electrodes” and 934 “electrode”- ¶0136);
a passivation layer 941 (“passivation layer”- ¶0137), located on the array substrate 920/934, wherein a first hole 961 (“hole”- ¶0137) corresponding to a resistance improvement area (i.e., the right area in Fig. 9F, analogous to the right area in Fig. 8, which has uniform electrical resistance for the cathode- ¶0126) is defined in the passivation layer 941;
a flat layer 942 (“flattening film”- ¶0138), located on the passivation layer 941, wherein a second hole 962 (“hole”- ¶0138) corresponding to the resistance improvement area is defined in the flat layer 942;
a second electrode layer 980 (“outgas reducing layer”, which comprises a conductive material- ¶0143), located on the flat layer 942, wherein a third hole (i.e., the space between the portions of 980) corresponding to the resistance improvement area is defined in the second electrode layer 980; and
a luminescent functional layer 950, located on an area of the second electrode layer 980 corresponding to a display area that is around the display area, the luminescent functional layer 950 comprising a luminescent layer 952 (“light emitting layer”- ¶0146), a cathode layer 953 (“cathode”- ¶0146), and an anode layer 951 (“anode”- ¶0142) connected to the first electrode layer 920/934 on the display area;
wherein the first hole 961, the second hole 964, and the third hole are connected, and a projection area of the first hole 961 (which includes undercut 970) on the array substrate 920/934 is greater than a projection area of the second hole 962 on the array substrate 920/934;
wherein a portion of the first electrode layer 920/934 on the resistance improvement area is located at a bottom of the first hole 961;
wherein the cathode layer 953 is connected to the second electrode layer 980 through the third hole, and connected to the first electrode layer 920/934 on the resistance improvement area through the second hole 962 and the first hole 962.
Regarding claim 2, Figure 9F of Heo discloses wherein a projection area of the second hole 962 on the array substrate 920/934 is greater than a projection area of the third hole on the array substrate 920/934.
Regarding claim 4, Figure 9F of Heo discloses the display panel further comprising:
a substrate 910 (“substrate”- ¶0135);
a third electrode layer 931 (“gate electrode”- ¶0135), located on the substrate 910; and
a dielectric layer 932 (“insulating film”- ¶0135), located on the third electrode layer 931;
wherein the first electrode layer 920/934 is located on the dielectric layer 932, and the first electrode layer 920/934 located in the resistance improvement area is parallel to the third electrode layer 931.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable and obvious over Heo.
Regarding claim 10, Figure 9F of Heo discloses wherein the second electrode layer 980 has a thickness.
Heo does not expressly disclose wherein the thickness of the second electrode layer ranges from 50 Å to 200 Å.
However, it would have been obvious to form the thickness of the second electrode layer within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Allowable Subject Matter
Claims 3, 5 and 7-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, the prior art of record including Heo, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein a concave notch on a side of the third hole is formed on the second electrode layer, and the cathode layer is connected to the second electrode layer through the concave notch”.
Regarding claim 5, the prior art of record including Heo, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “[the] display panel… further comprising a capacitance area located around the display area, wherein the first electrode layer and the second electrode layer located in the capacitance area form an auxiliary capacitor”.
Regarding claim 7, the prior art of record including Heo, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “[the] display panel… further comprising a packaging area located on a side of the resistance improvement area far from the display area, and no flat layer is formed on the packaging area”.
Regarding claim 8, the prior art of record including Heo, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein the flat layer is not formed on a junction of the resistance improvement area and the display area”.
Regarding claim 9, the prior art of record including Heo, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein the anode layer comprises a first anode layer and a second anode layer, the first anode layer is located on the second electrode layer, the second anode layer is located on the first anode layer, the luminescent layer is located on the second anode layer, and the first anode layer is electrically connected to the first electrode layer”.
Claim 6 (which depends from claim 5, which includes allowable subject matter) would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 11-15 and 17-20 are allowed.
Regarding independent claim 11, Figure 9F of Heo discloses a display panel, comprising:
an array substrate 920/934 (collectively 920 and 934), comprising a first electrode layer 920/934 (collectively 920 “electrodes” and 934 “electrode”- ¶0136);
a passivation layer 941 (“passivation layer”- ¶0137), located on the array substrate 920/934, wherein a first hole 961 (“hole”- ¶0137) corresponding to a resistance improvement area (i.e., the right area in Fig. 9F, analogous to the right area in Fig. 8, which has uniform electrical resistance for the cathode- ¶0126) is defined in the passivation layer 941;
a flat layer 942 (“flattening film”- ¶0138), located on the passivation layer 941, wherein a second hole 962 (“hole”- ¶0138) corresponding to the resistance improvement area is defined in the flat layer 942;
a second electrode layer 980 (“outgas reducing layer”, which comprises a conductive material- ¶0143), located on the flat layer 942, wherein a third hole (i.e., the space between the portions of 980) corresponding to the resistance improvement area is defined in the second electrode layer 980; and
a luminescent functional layer 950, located on an area of the second electrode layer 980 corresponding to a display area that is around the display area, the luminescent functional layer 950 comprising a luminescent layer 952 (“light emitting layer”- ¶0146), a cathode layer 953 (“cathode”- ¶0146), and an anode layer 951 (“anode”- ¶0142) connected to the first electrode layer 920/934 on the display area;
wherein the cathode layer 953 is connected to the first electrode layer 920/934 on the resistance improvement area through the second hole 962 and the first hole 961, and the cathode layer 953 is connected to the second electrode layer 980 through the third hole and the concave notch.
Heo does not expressly disclose a concave notch on a side of the third hole is formed on the second electrode layer and wherein the cathode layer is connected to the second electrode layer through the concave notch.
Thus, regarding independent claim 11, the claim is allowed, because the prior art of record including Heo, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “a concave notch on a side of the third hole is formed on the second electrode layer” and “the cathode layer is connected to the second electrode layer through the third hole and the concave notch”.
Claims 12-15 and 17-20 are allowed as being dependent on allowed claim 11.
Claim 16 (which depends from allowed claim 11) would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lee et al. (US 2023/0189572 A1), which discloses a display device comprising a cathode electrode connected to a first electrode layer through a hole.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAY C CHANG/Primary Examiner, Art Unit 2817