DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 8/21/2024, 12/13/2024 and 10/21/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation “its bonding surface” in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 5 recites the abbreviation “RF” in line 3 of the claim, however the expanded form of the abbreviation has not been clearly defined and thereby it is unclear what is necessarily required by the abbreviation “RF”.
Note the dependent claims 3-4 necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 5-10 and 12-18 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2021/0151388 A1, hereinafter “Choi”) in view of Wang et al. (US 2003/0122241 A1, hereinafter “Wang”).
PNG
media_image1.png
677
1145
media_image1.png
Greyscale
Regarding independent claim 1, Figures 1A-1C of Choi disclose a semiconductor package, comprising:
a package substrate 10 (“substrate”- ¶0025);
an interposer 20 (“interposer”- ¶0025) disposed on and electrically connected to the package substrate 10;
at least one central logic die 31 (“logic chips”- ¶0025) disposed on and electrically connected to the interposer 20;
a plurality of peripheral function dies 41a-41d (“memory stacks”- ¶0028) disposed on and electrically connected to the interposer 20 and located in proximity to the at least one central logic die 31;
at least one dummy die 51a (“stiffening chips… dummy chip”- ¶0037) disposed between the at least one central logic die 31 and the plurality of peripheral function dies 41a-41d (Note, a portion of die 51a is disposed between portions of die 41b and die 31 in a diagonal direction as indicated by the dotted line as shown above in Examiner’s Markup Fig. 1A Choi) so as to form a rectangular shaped die arrangement (i.e., specifically the rectangular shape notated as “Die Arrangement”; see above Examiner’s Markup Fig. 1A Choi), wherein the at least one dummy die 51a is disposed at a corner position of the rectangular shaped die arrangement;
a first underfill 72 (“underfill”- ¶0037) filling a gap between the at least one central logic die 31 and the interposer 20, a gap between the plurality of peripheral function dies 41a-41d and the interposer 20, a gap between the at least one dummy die 51a and the interposer 20;
an epoxy molding compound 80 (“epoxy molding compound”- ¶0042) encapsulating the at least one central logic die 31, the plurality of peripheral function die 41a-41d, and the at least one dummy die 51a; and
a second underfill 71 (“underfill”- ¶0037) filling a gap between the interposer 20 and the package substrate 10.
Choi does not expressly disclose the first underfill filling a gap between the at least one central logic die and the plurality of peripheral function dies, and a gap between the at least one central logic die and the at least one dummy die.
Figure 5 of Wang discloses a semiconductor package comprising a die 250 (“chips”- ¶0017) and an underfill 100 (“underfill”- ¶0015), wherein the underfill 100 fills a gap between the die 250 and an interposer 400 (“substrate”- ¶0040) and further covers sidewalls of the die 250 to form protective side portions 550 (“protective side portions”- ¶0040).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Choi such that the first underfill further covers the sidewalls of the at least one central logic die, the plurality of peripheral function dies, and the at least one dummy die (analogous to the die in Wang) to form protective side portions as taught by Wang for the purpose of utilizing a suitable and well-known configuration of the underfill which protects the sidewalls of the dies (Wang ¶0040).
Thus, the combined teachings including Wang would disclose the first underfill filling a gap between the at least one central logic die and the plurality of peripheral function dies, and a gap between the at least one central logic die and the at least one dummy die, because the first underfill would further cover the sidewalls of the dies such that the first underfill would fill in portions of the gaps between the respective dies as required by the claim limitation.
Regarding claim 5, Figures 1A-1C of Choi disclose wherein the at least one central logic die 31 comprises a system-on-chip (SoC), a central processing unit (CPU) die, a graphic processing unit (GPU) die, an RF die, or an application processor (AP) die (¶0027).
Regarding claim 6, Figures 1A-1C of Choi disclose wherein the plurality of peripheral function dies 41a-41d comprises memory dies (¶0025).
Regarding claim 7, Figures 1A-1C of Choi disclose wherein the at least one dummy die 51a comprises a silicon die (¶0037).
Regarding claim 8, Figures 1A-1C of Choi disclose wherein the at least one dummy die 51a comprises ceramic, metal, polymer, or thermal conductive materials (¶0037).
Regarding claim 9, Figures 1A-1C of Choi disclose a size of the interposer 20.
Choi does not expressly disclose wherein the size of the interposer is greater than 1.5 reticle size, wherein 1 reticle size is 26mm × 34mm.
However, it would have been obvious to form the size of the interposer within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 10, Figures 1A-1C of Choi disclose wherein the interposer 20 comprises a silicon interposer (¶0026) and comprises a plurality of through silicon vias 26 (“interposer vias”- ¶0040).
Regarding claim 12, Figures 1A-1C of Choi disclose wherein the at least one central logic die 31, the plurality of peripheral function dies 41a-41d, and the at least one dummy die 51a have substantially the same die thickness.
Regarding claim 13, Figures 1A-1C of Choi disclose wherein the at least one central logic die 31 is mounted on the interposer 20 through first micro-bumps 63 (“chip bumps”- ¶0037), the plurality of peripheral function dies 41a-41d is mounted on the interposer 20 through second micro-bumps 63 (“chip bumps”- ¶0037), and the at least one dummy die 51a is mounted on the interposer 20 through third micro-bumps 63 (“chip bumps”- ¶0037).
Regarding claim 14, Figures 1A-1C of Choi disclose wherein the first, second, and third micro-bumps 63 are surrounded by the first underfill 72.
Regarding claim 15, Figures 1A-1C of Choi disclose wherein the interposer 20 is connected to the package substrate 10 through flip chip bumps 62 (“interposer bumps”- ¶0037) or C4 bumps.
Regarding claim 16, Figures 1A-1C of Choi disclose wherein the flip chip bumps 62 or C4 bumps are surrounded by the second underfill 71.
Regarding claim 17, Figures 1A-1C (as implemented with the stiffening dam 55 shown in Figs. 2A-2B) of Choi disclose the semiconductor package further comprising:
a stiffener ring 55 (“stiffening dam”- ¶0048) mounted on a top surface of the package substrate 10.
Regarding claim 18, Figures 1A-1C (as implemented with the stiffening dam 55 shown in Figs. 2A-2B) of Choi disclose wherein the stiffener ring 55 comprises metal (¶0048).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over the combined teachings of Choi and Wang in further view of Sakuma et al. (US 2023/0197657 A1, hereinafter “Sakuma”).
Regarding claim 11, Figures 1A-1C of Choi disclose wherein the interposer 20 comprises glass or silicon (¶0026).
Choi does not expressly disclose wherein the interposer comprises organic material.
Figure 2 of Sakuma discloses a semiconductor package comprising an interposer 220 (“interposer”- ¶0040), wherein the interposer 220 comprises glass, silicon, or an organic material (¶0040).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings such that the interposer comprises organic material as taught by Sakuma for the purpose of substituting art recognized equivalents known to be used for the same purpose (MPEP 2144.06), specifically utilizing a suitable and generally known interposer material (Sakuma ¶0040).
Allowable Subject Matter
Claims 2-4 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claim 2 (which claims 3-4 depend from), the prior art of record including Choi and/or Wang, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein the at least one dummy die comprises an adhesion polymer layer disposed on its bonding surface”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Shih et al. (US 2016/0358865 A1), which discloses a semiconductor package comprising a plurality of dies formed on an interposer and an underfill filling a gap between the dies and the interposer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAY C CHANG/Primary Examiner, Art Unit 2817