DETAILED ACTION
Priority Claim
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
IDS
All references provided in the IDS filed on 12/27/2023, 01/28/2025, and 05/18/2026 have been considered.
Election/Restrictions
Applicant’s election without traverse of Species E (Fig. 24) in the reply filed on 05/20/2026 is acknowledged. Claims 4, 6, 7, 8, 9, 14, 17, 18 are withdrawn as they are drawn to non-elected species.
Specification
The disclosure is objected to because of the following informalities: missing/inconsistent reference numeral usage.
In the specification, for example ¶ [0047], reference numerals are missing for the “base region.” Furthermore, in ¶ [0069], for example, “base region” is also denoted with the reference numeral ’14-e’. Furthermore, also in ¶ [0069], “base regions” is also denoted with the reference numeral ’14-e’. The relationship between base region (14), base region (14-e), and base regions (14-e) is unclear.
In the specification, for example ¶ {0059] and [0060], reference numerals are missing for the ‘gate conductive portion’.
There may be more examples of missing/inconsistent reference numerals usage, applicant is kindly requested to correct/verify the reference numerals in the specification to maintain clarity.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-3, 5, 10-13, 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding Independent Claim 1,
Claim 1, lines 13-15 recite: “the isolation region has a second lower end region of the second conductivity type that is provided to be in contact with lower ends of one or more trench portions including the gate trench portion”. The scope of the claim is unclear as it cannot be precisely determined what the second lower end region contacts. The trench portion already includes a gate trench portion and a dummy trench portion, so as written “the lower end of one or more trench portions” could mean the second lower end region contacts the gate trench and/or the dummy gate trench. The extra inclusion of “including the gate trench portion” does not specify whether the second lower end region especially contacts the gate trench portion and the dummy portion, or only the gate trench portion. It has been interpreted to mean that the second lower end region contacts any portion of the plurality of trenches. Claims 1-3, 5, 10-13, 15-16, 19 are rejected by virtue of their dependency on Claim 1.
Regarding Dependent Claim 2,
Claim 2, line 1 recites: “the number of the trench portions”
There is insufficient antecedent basis for this limitation in the claim as no “a number of trench portions” has been claimed. It has been interpreted to mean “the plurality of trench portions”.
Regarding Dependent Claim 2,
Claim 2, line 2 recites: “in contact with one of second lower end regions”
There is insufficient antecedent basis for this limitation in the claim as no plurality of second lower end regions has been claimed. It is unclear how the plurality of trench portions are arranged with the one second lower end region. It has been interpreted to mean a trench portion contacts a second lower end region.
Regarding Dependent Claim 2,
Claim 2, line 2 recites: “each being identical to the second lower end region”. There is insufficient antecedent basis for this limitation in the claim as no plurality of second lower end regions is claimed, it is unclear what is to be identical to the claimed second lower end region. It has been interpreted to mean that there is a second lower end region.
Regarding Dependent Claim 2,
Claim 2, line 3 recites: “less than the number of trench portions in contact with”. There is insufficient antecedent basis for this limitation in the claim as no “a number of trench portion in contact with” has been claimed. It has been interpreted to mean “a number of trench portions in contact with”.
Regarding Dependent Claim 2,
Claim 2, line 3 recites: “in contact with one of first lower end regions”
There is insufficient antecedent basis for this limitation in the claim as no plurality of first lower end regions has been claimed. It is unclear how the plurality of trench portions are arranged with the one first lower end region. It has been interpreted to mean a trench portion contacts a first lower end region.
Regarding Dependent Claim 2,
Claim 2, lines 3-4 recites: “each being identical to the first lower end region”
As no plurality of first lower end regions is claimed, it is unclear what is to be identical to the claimed first lower end region. It has been interpreted to mean that there is a first lower end region.
Regarding Dependent Claim 3,
Claim 3, lines 1 recites: “one of second lower end regions”
There is insufficient antecedent basis for this limitation in the claim as no plurality of second lower end regions has been claimed. It has been interpreted to mean “a second lower end region”. Claims 5 and 10 are rejected by virtue of its dependency on Claim 3.
Regarding Dependent Claim 3,
Claim 3, lines 1-2 recites: “each being identical to the second lower end region”. There is insufficient antecedent basis for this limitation in the claim as no plurality of second lower end regions is claimed, it is unclear what is to be identical to the claimed second lower end region. It has been interpreted to mean that there is a second lower end region. Claims 5 and 10 are rejected by virtue of its dependency on Claim 3.
Regarding Dependent Claim 3,
Claim 3, line 2-3 recites: “is in contact with a lower end of one of gate trench portions”. There is insufficient antecedent basis for this limitation in the claim as no plurality of gate trench portions is claimed. It has been interpreted to mean a second lower end region contacts a trench portion. Claims 5 and 10 are rejected by virtue of its dependency on Claim 3.
Regarding Dependent Claim 3,
Claim 3, line 3 recites: “each being identical to the gate trench portion”. There is insufficient antecedent basis for this limitation in the claim as no plurality of gate trench portions is claimed. It is unclear what is to be identical to the claimed gate trench portion. It has been interpreted to mean that there is a trench portion. Claims 5 and 10 are rejected by virtue of its dependency on Claim 3.
Regarding Dependent Claim 3,
Claim 3, lines 3-4 recites: “and is not in contact with a lower end of the gate trench portion other than that of the one of the gate trench portions”. As no plurality of gate trench portions is claimed, it is unclear how a single gate trench portion is in contact with a second lower end region and also not in contact with a second lower end region. It has been interpreted to mean that a trench portion contacts a second lower end region. Claims 5 and 10 are rejected by virtue of its dependency on Claim 3.
Regarding Dependent Claim 5,
Claim 5, lines 1 recites: “one of the second lower end regions”
There is insufficient antecedent basis for this limitation in the claim as no plurality of second lower end regions has been claimed. It has been interpreted to mean “a second lower end region”.
Regarding Dependent Claim 5,
Claim 5, lines 1-2 recites: “each being identical to the second lower end region”. There is insufficient antecedent basis for this limitation in the claim as no plurality of second lower end regions is claimed, it is unclear what is to be identical to the claimed second lower end region. It has been interpreted to mean that there is a second lower end region.
Regarding Dependent Claim 5,
Claim 5, line 2-3 recites: “is in contact with a lower end of one of gate trench portions”. There is insufficient antecedent basis for this limitation in the claim as no plurality of gate trench portions is claimed. It has been interpreted to mean a second lower end region contacts a trench portion.
Regarding Dependent Claim 5,
Claim 5, line 3 recites: “each being identical to the gate trench portion”. There is insufficient antecedent basis for this limitation in the claim as no plurality of gate trench portions is claimed. It is unclear what is to be identical to the claimed (singular) gate trench portion. It has been interpreted to mean that there is a trench portion.
Regarding Dependent Claim 5,
Claim 5, line 4 recites: “lower end of the trench portion”. There is insufficient antecedent basis for this limitation in the claim as no singularity of a trench portion is claimed. In the plurality of trench portions, it is unclear which constitutes “the trench portion”. It has been interpreted to mean “lower end of at least of one the trench portions…”.
Regarding Dependent Claim 10,
Claim 10, line 5 recites: “the gate conductive portion at at least one among the among the gate trench portions”. There is insufficient antecedent basis for this limitation in the claim as no plurality of gate trench portions is claimed. It has been interpreted to mean “the gate conductive portion in contact with the trench portion”.
Regarding Dependent Claim 11,
Claim 11, line 2 recites: “two or more of the dummy trench portions”. There is insufficient antecedent basis as no plurality of dummy trench portions has been claimed. It has been interpreted to mean “two or more trench portions”.
Regarding Dependent Claim 11,
Claim 11, line 7 recites: “two or more of the dummy trench portions”. There is insufficient antecedent basis as no plurality of dummy trench portions has been claimed. It has been interpreted to mean “two or more trench portions”.
Regarding Dependent Claim 12,
Claim 12, line 5 recites: “at at least one of the gate trench portions”. There is insufficient antecedent basis for this limitation in the claim as no plurality of gate trench portions is claimed. It has been interpreted to mean “at least one of the trench portions”.
Regarding Dependent Claim 12,
Claim 12, lines 6-8 recites: “the gate conductive portion at a position in contact with the in contact with the gate dielectric film is longer than the gate conductive portion at a position that is the farthest from the gate dielectric film in a depth direction”. As the gate conductive portion contacts the gate dielectric film in multiple positions, the scope of the claim is unclear. It has been interpreted to mean the gate dielectric film surrounds the gate conductive portion.
Regarding Dependent Claim 13,
Claim 13, line 1 recites: “wherein at least one of the gate trench portions”. There is insufficient antecedent basis for this limitation in the claim as no plurality of gate trench portions has been claimed. It has been interpreted to mean “at least of one the trench portions”.
Regarding Dependent Claim 19,
Claim 19, line 1 recites: “two or more of the gate trench portions.” There is insufficient antecedent basis as no plurality of gate trench portions has been claimed. It has been interpreted to mean “two or more trench portions”.
Regarding Dependent Claim 19,
Claim 19, line 1 recites “the second lower region being separated from each other is provided”. The scope of the claim is unclear, as this claim, as written suggests multiple second lower regions, although a plurality of second lower end regions has not been claimed. It has been interpreted to mean that there is a second lower end region.
Regarding Dependent Claim 20,
Claim 20, lines 11-13 recites “the gate trench portion in contact with the second lower end region is shorter than at least another one of the gate trench portions, each being identical to the gate trench portion in a depth direction”. The scope of the claim is unclear as the shortened gate trench portion would not be identical to the gate trench portion. It has been interpreted to mean there is a trench portion.
Regarding Dependent Claim 20,
Claim 20, line 12 recites “one of gate trench portions”. There is insufficient antecedent basis for this claim limitation as no plurality of gate trench portions has been claimed. It has been interpreted to mean “one of the trench portions”.
Regarding Dependent Claim 20,
Claim 20, line 12 recites “each being identical to the gate trench portion”. There is insufficient antecedent basis for this limitation in the claim as no plurality of gate trench portions is claimed. It is unclear what is to be identical to the claimed (singular) gate trench portion. It has been interpreted to mean that there is a trench portion.
In light of the multiple 112b issues, all claims are given their broadest most reasonable interpretation.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, 12, 19 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Hirler (US 9252251 B2).
Re: Independent Claim 1, Hirler discloses:
A semiconductor device (Hirler, a semiconductor component, Col. 1, line 55) comprising:
a semiconductor substrate (Hirler, semiconductor body; Fig. 3, element 100) that has an upper surface (Hirler, first side; Fig. 3, element 101) and a lower surface (Hirler, second side; Fig. 3, element 102), and includes a drift region (Hirler, drift zone; Fig. 3, element 13) of a first conductivity type (Hirler, drift zone has conductivity type n, which is the first conductivity type);
a base region (Hirler, body zone, Fig. 3, element 12) of a second conductivity type (Hirler, body zone (element 12) has conductivity type p, which is the second conductivity type) that is provided between the drift region and the upper surface of the semiconductor substrate;
a plurality of trench portions (Hirler, trench; Fig. 3, element 19 and element 25, multiple are shown) that are provided from the upper surface of the semiconductor substrate to below the base region, and include a gate trench portion (Hirler, trenches; Fig. 3, element 19, 25) and a dummy trench portion (Hirler, trenches; Fig. 4, element 25);
a first lower end region (Hirler, second partial layer; Fig. 12, element 103", the left side of this contained within the inner region (element 105), can be considered a first lower end region) of the second conductivity type (Hirler, Col. 8, lines 55 - 58) that is provided to be in contact with lower ends of two or more trench portions which include the gate trench portion (Hirler, Fig. 12); and
an isolation region (Hirler, second partial layer; Fig. 7, element 103", the right side of this contained within the edge region (element 106) can be considered an isolation region) that is not overlapped with the first lower end region in a top view, wherein
the isolation region has a second lower end region (Hirler, first edge zone, Fig. 6C + Fig. 6D, element 21) of the second conductivity type that is provided to be in contact with lower ends of one or more trench portions including the gate trench portion.
Re: Dependent Claim 2, Hirler disclose(s) all the limitations of claim 1 on which this claim depends. Hirler further discloses:
wherein the number of the trench portions (Hirler, trench; Fig. 2, element 19 and element 25, multiple are shown) in contact with one of second lower end regions (Hirler, first edge zone, Fig. 2, element 21), each being identical to the second lower end region (Hirler, Fig. 2, element 21 is identical to element 21).
Re: Dependent Claim 3, Hirler disclose(s) all the limitations of claim 1 on which this claim depends. Hirler further discloses:
wherein one of second lower end regions (Hirler, first edge zone, Fig. 6C, element 21), each being identical to the second lower end region (Hirler, Fig. 2, element 21 is identical to element 21 in Fig. 6C), is in contact with a lower end of one of gate trench portions (Hirler, trenches; Fig. 3, element 19, 25) each being identical to the gate trench portion (Hirler, Fig. 6C, element 25 is dimensionally identical to element 19), and is not in contact with a lower end of the gate trench portion other than that of the one of the gate trench portions (Hirler, Fig. 6C, element 21 is not in contact with any other gate trench portions).
Re: Dependent Claim 5, Hirler disclose(s) all the limitations of claim 3 on which this claim depends. Hirler further discloses:
wherein one of the second lower end regions (Hirler, first edge zone, Fig. 6C, element 21), each being identical to the second lower end region (Hirler, Fig. 2, element 21 is identical to element 21 in Fig. 6C), is in contact with a lower end of one of the gate trench portions (Hirler, trenches; Fig. 3, element 19, 25), each being identical to the gate trench portion (Hirler, Fig. 6C, element 25 is dimensionally identical to element 19), and is not in contact with a lower end of the trench portion (Hirler, trench; Fig. 6C, element 19) that is arranged adjacent to the gate trench portion (Hirler, Fig. 6C, elements 21 and 19 do not contact each other).
Re: Dependent Claim 12, Hirler disclose(s) all the limitations of claim 1 on which this claim depends. Hirler further discloses:
wherein the gate trench portion includes (Hirler, trenches; Fig. 7, element 19, 25):
a gate dielectric film (Hirler, dielectric layer; Fig. 7, element 24); and
a gate conductive portion (Hirler, connecting edge electrode; Fig. 7, element 23) that is insulated from the semiconductor substrate by the gate dielectric film (Hirler, Col. 6, lines 1-16), wherein
at at least one of the gate trench portions (Hirler, trenches; Fig. 3, element 19, 25) in contact with the second lower end region (Hirler, first edge zone, Fig. 7, element 21), the gate conductive portion at a position in contact with the gate dielectric film is longer than the gate conductive portion at a position that is the farthest from the gate dielectric film in a depth direction (Hirler, Fig. 7).
Re: Dependent Claim 19, Hirler disclose(s) all the limitations of claim 1 on which this claim depends. Hirler further discloses:
wherein for each of two or more of the gate trench portions (Hirler, trenches; Fig. 7, element 19, 25), the second lower end region (Hirler, first edge zone, Fig. 7, element 21) being separated from each other is provided.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Hirler (US 9252251 B2) in view of Kawashima (US 20080001217 A1).
Re: Dependent Claim 10, Hirler disclose(s) all the limitations of claim 3 on which this claim depends. Hirler further discloses:
wherein the gate trench portion includes (Hirler, trenches; Fig. 7, element 19, 25):
a gate dielectric film (Hirler, dielectric layer; Fig. 7, element 24); and
a gate conductive portion (Hirler, connecting edge electrode; Fig. 7, element 23) that is insulated from the semiconductor substrate by the gate dielectric film (Hirler, Col. 6, lines 1-16), wherein
the gate conductive portion at at least one among the gate trench portions in contact with the second lower end region (Hirler, first edge zone, Fig. 7, element 21 indirectly contacts element 23)
Hirler does not explicitly disclose:
the second lower end region is shorter than the gate conductive portion of the gate trench portion in contact with the first lower end region in a depth direction.
Kawashima discloses:
wherein the gate conductive portion (Kawashima, connecting electrode; Fig. 12, element 109a) at at least one among the gate trench portions (Kawashima, first trench, second trench; Fig. 12, elements 141 and 142, respectively, make up the gate trench portions) in contact with the second lower end region (Kawashima, p-type guard region; Fig. 12, element 130) is shorter than the gate conductive portion (Kawashima, gate electrode; Fig. 12, element 108) of the gate trench portion in contact with the first lower end region (Kawashima, p-type column regions; Fig. 12, element 106) in a depth direction (Kawashima, Fig. 12, the up/down direction can be considered a depth direction, 109a is shorter than 108).
Hirler discloses a gate trench portion in contact with the second lower end region, but does not explicitly disclose that the gate conductive portion of the gate trench in contact with the second lower end region is shorter than the gate conductive portion of the gate trench in contact with the first lower end region. Kawashima discloses a gate conductive portion of a gate trench in contact with a second lower end region that is shorter than a gate conductive portion of a gate trench in contact with a first lower end region for use in a semiconductor device. Hirler and Kawashima disclose use of trenches and lower end regions for use in a semiconductor device and are therefore analogous art. It would be obvious to a person of ordinary skill in the art (POSITA) before the effective filing date to use the gate trench structure of Kawashima in the device of Hirler for the benefit of voltage control (Kawashima, ¶ [0083]).
Claim 13 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Hirler (US 9252251 B2) in view of Takaya (US 7470953 B2).
Re: Dependent Claim 13, Hirler disclose(s) all the limitations of claim 1 on which this claim depends. Hirler further discloses:
wherein at least one of the gate trench portions (Hirler, trenches; Fig. 7, element 19, 25) in contact with the second lower end region (Hirler, first edge zone, Fig. 7, element 21)
Hirler does not explicitly disclose:
with the second lower end region is shorter than the gate trench portion in contact with the first lower end region in a depth direction.
Takaya discloses:
wherein at least one of the gate trench portions (Takaya, gate trench; Fig. 13, element 21) in contact with the second lower end region (Takaya, P floating region; Fig. 13, element 51) is shorter than the gate trench portion in contact with the first lower end region (Takaya, P floating region; Fig. 13, element 54) in a depth direction (Takaya, the up/down direction can be considered a depth direction).
Hirler discloses a gate trench portion in contact with the second lower end region, but does not explicitly disclose that the gate trench portion in contact with the second lower end region is shorter than the gate trench portion in contact with the first lower end region. Takaya discloses a gate trench portion in contact with the second lower end region that is shorter than the gate trench portion in contact with the first lower end region in a depth direction for use in a semiconductor device. Both Hirler and Takaya disclose the usage of trenches in a semiconductor device and are therefore analogous art. It would be obvious to a POSITA before the effective filing date to use the gate trenches and regions of Takaya in the device of Hirler for the benefit of spreading out the regions and obtain an optimum high withstand voltage design (Takaya, Col. 14, lines 9-25).
Claims 15-16 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hirler (US 9252251 B2) in view of Ozaki (US 20200357904 A1).
Re: Dependent Claim 15, Hirler disclose(s) all the limitations of claim 1 on which this claim depends. Hirler further discloses:
a semiconductor substrate (Hirler, semiconductor body; Fig. 3, element 100) that has an upper surface (Hirler, first side; Fig. 3, element 101)
Hirler is silent regarding:
further comprising: an emitter region of the first conductivity type that is exposed on the upper surface of the semiconductor substrate, is provided to be in contact with the gate trench portion, and has a doping concentration higher than that of the drift region; and a contact region of the second conductivity type that is exposed on the upper surface of the semiconductor substrate, is alternately arranged with the emitter region along a longitudinal direction of the gate trench portion, and has a doping concentration higher than that of the base region;
Ozaki discloses:
further comprising:
an emitter region (Ozaki, emitter region; Fig. 3, element 12) of the first conductivity type (Ozaki, n-type is the first conductivity type; ¶ [0050]) that is exposed on the upper surface of the semiconductor substrate (Ozaki, semiconductor substrate; Fig. 3, element 10), is provided to be in contact with the gate trench portion (Ozaki, gate trench; Fig. 3, element 40), and has a doping concentration higher than that of the drift region (Ozaki, drift region; Fig. 3, element 18, ¶ [0039], drift region is N- while emitter region is N+); and
a contact region (Ozaki, contact region; Fig. 2, element 15) of the second conductivity type (Ozaki, contact region is P+ type; ¶ [0051]) that is exposed on the upper surface of the semiconductor substrate (Ozaki, ¶ [0051]), is alternately arranged with the emitter region along a longitudinal direction of the gate trench portion (Ozaki, Fig. 2, shows element 12 and 15 alternatively arranged along a longitudinal direction of the gate trench portion), and has a doping concentration higher than that of the base region (Ozaki, base region; Fig. 3, element 14, ¶ [0039], base region is denoted P-, while contact region is P+);
Hirler discloses a semiconductor device, but does not explicitly disclose an emitter region of the first conductivity type that is exposed on the upper surface of the semiconductor substrate, is provided to be in contact with the gate trench portion, and has a doping concentration higher than that of the drift region; and a contact region of the second conductivity type that is exposed on the upper surface of the semiconductor substrate, is alternately arranged with the emitter region along a longitudinal direction of the gate trench portion, and has a doping concentration higher than that of the base region; wherein the second lower end region is arranged to overlap with the emitter region in a top view. Ozaki discloses an emitter region of the first conductivity type that is exposed on the upper surface of the semiconductor substrate in contact with the gate trench portion, and has a doping concentration higher than that of the drift region; and a contact region of the second conductivity type that is exposed on the upper surface of the semiconductor substrate, is alternately arranged with the emitter region along a longitudinal direction of the gate trench portion, and has a doping concentration higher than that of the base region; wherein the second lower end region is arranged to overlap with the emitter region in a top view. Both Hirler and Ozaki disclose semiconductor devices with elements such as trenches and semiconductor substrates. In the absence of any criticality, it would be obvious to a POSITA before the effective filing date, to include the corresponding structural features like an emitter region, contact region, and collector region, as taught by Ozaki, to the device structure of Hirler. Including an emitter region and contact region with the disclosed conductivity types and configurations is matter of routine/known design choice in semiconductor device configurations which include trenches used in semiconductor device connections used (Ozaki, ¶ [0058]) and yields predictable results of forming a known semiconductor device.
Hirler, as modified by Ozaki, further discloses:
further comprising a collector region (Ozaki, collector region; Fig. 3, element 22) of the second conductivity type (Ozaki, Fig. 3, P-type is the second conductivity type) that is provided to be in contact with the lower surface of the semiconductor substrate (Ozaki, semiconductor substrate Fig. 3, element 10).
Re: Dependent Claim 16, Hirler and Ozaki disclose(s) all the limitations of claim 15 on which this claim depends. Hirler, as modified by Ozaki, further discloses:
further comprising a collector region (Ozaki, collector region; Fig. 3, element 22) of the second conductivity type (Ozaki, Fig. 3, P-type is the second conductivity type) that is provided to be in contact with the lower surface of the semiconductor substrate (Ozaki, semiconductor substrate Fig. 3, element 10).
Claim 20 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Ozaki (US 20200357904 A1) in view of Takaya (US 7470953 B2).
Re: Independent Claim 20,
A semiconductor device comprising (Ozaki, semiconductor device; Fig. 3, element 100): a semiconductor substrate (Ozaki, semiconductor substrate; Fig. 3, element 10) that has an upper surface (Ozaki, Fig. 3, the top surface of element 10 can be considered an upper surface) and a lower surface (Ozaki, Fig. 3, the bottom surface of element 10 can be considered a lower surface), and includes a drift region of a first conductivity type (Ozaki, drift region; Fig. 3, element 18, ¶ [0039], drift region is N-type);
a base region of a second conductivity type (Ozaki, base region; Fig. 3, element 14, ¶ [0039], base region is denoted P-) that is provided between the drift region and the upper surface of the semiconductor substrate;
a plurality of trench portions (Ozaki, gate trench portion, dummy trench portion; Fig. 3, elements 40 and 30, respectively, make up a plurality of trench portions) that are provided from the upper surface of the semiconductor substrate to below the base region, and include a gate trench portion (Ozaki, gate trench portion; Fig. 3, element 40) and a dummy trench portion (Ozaki, dummy trench portion; Fig. 3, element 30); and
Ozaki does not disclose:
and a second lower end region of the second conductivity type that is provided to be in contact with lower ends of one or more trench portions including the gate trench portion, wherein the gate trench portion in contact with the second lower end region is shorter than at least another one of gate trench portions, each being identical to the gate trench portion, in a depth direction.
Takaya discloses:
and a second lower end region of the second conductivity type (Takaya, P floating region; Fig. 13, element 51) that is provided to be in contact with lower ends of one or more trench portions (Takaya, trenches; Fig. 3, elements 21, 25, make up one or more trench portions) including the gate trench portion (Takaya, gate trench; Fig. 13, element 21), wherein
the gate trench portion in contact with the second lower end region is shorter than at least another one of gate trench portions, each being identical to the gate trench portion, in a depth direction (Takaya, Fig. 3).
Ozaki discloses a semiconductor device, a drift region, a base region, gate trench portions and dummy portions, but Ozaki does not disclose a second lower end region in contact with a gate trench portion that is shorter than one other gate trench portion. Takaya discloses trenches connected to a second lower end region that is shorter than one other gate trench portion. Both Ozaki and Takaya disclose semiconductor devices, gate trenches, and their configurations and are therefore analogous art. It would be obvious to a POSITA before the effective filing date to include the gate trench that is shorter with the second lower end region with the second conductivity type, as disclosed by Takaya, to the device of Ozaki, for the benefit of spreading out the regions and obtain an optimum high withstand voltage design (Takaya, Col. 14, lines 9-25).
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re: Claim 11, the prior art of record do not disclose or suggest, in combination with all other limitations in the claim:
Two or more of the dummy trench portions that are not in contact with the first lower end region and the second lower region are arranged in series adjacent to the gate trench portion that is in contact with the first lower end region; and the semiconductor device further comprises a fourth lower end region of the second conductivity type that is provided to be in contact with the lower ends of the two or more of the dummy trench portions arranged in series.
The prior art disclosed and made of record do not suggest, disclose, or give motivation to include/combine a fourth lower end region that has two dummy trench regions in series that do not contact other end regions.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
Naito (US-10319808-B2) and Sakurai (US-20240120413-A1) disclose semiconductor devices with gate trench portions, dummy trench portions and their configurations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIMARTA KAUR CHOWDHARY whose telephone number is (571)272-7679. The examiner can normally be reached usually Monday - Thursday, 6:45 AM - 4:45 PM (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIMARTA KAUR CHOWDHARY/ Examiner, Art Unit 2898
/Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898
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