Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2022-0180892, filed on 12/21/2021.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/18/2023is in compliance
with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being
considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Regarding claim 1, in Step 1 of the 101 analyses set forth in MPEP 2106, the claim recites A method comprising. A method is one of the four statutory categories.
In Step 2a Prong 1 of the 101 analyses set forth in the MPEP 2106, the examiner has determined that the following limitations recite a process that, under the broadest reasonable interpretation, covers a [ mental process/mathematical concept] but for recitation of generic computer components:
generating a plurality of partial layouts based on the layout data; (A person can mentally generate a plurality of partial layouts based on layout data by a process of simply evaluating the layout data and making a judgement on how to create the partial layout.)
selecting a representative partial layout among the plurality of partial layouts; (A person can mentally select a representative partial layout among the plurality of partial layouts by a process of simply evaluating the partial layouts and making a judgement on which partial layout is the most representative.)
and generating, …, a predicted measurement result for the semiconductor based on the representative partial layout. (A person can mentally generate a predicted measurement result based on a representative partial layout by a process of simply evaluating the partial layout and making a judgment on what the measurement results will be.)
If claim limitations, under their broadest reasonable interpretation, covers performance of the limitations as a [ mental process/mathematical concept] but for the recitation of generic computer components, then it falls within the mental process grouping of abstract ideas. According, the claim “recites” an abstract idea.
In Step 2a Prong 2 of the 101 analyses set forth in MPEP 2106, the examiner has determined that the following additional elements do not integrate this judicial exception into a practical application:
receiving layout data representing a layout of a semiconductor; (Adding insignificant extra-solution activity (mere data gathering) to the judicial exception (MPEP 2106.05(g))).
…using a machine learning model… (Uses a computer as a tool to perform an abstract idea (MPEP 2106.05(f))).
Since the claim does not contain any other additional elements that are indicative of integration into a practical application, the claim is “directed” to an abstract idea.
In Step 2b of the 101 analyses set forth in the 2019 PEG, the examiner has determined that the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
receiving layout data representing a layout of a semiconductor; (Adding insignificant extra-solution activity (mere data gathering) to the judicial exception (MPEP 2106.05(g)) Furthermore, the additional element is directed to receiving or transmitting data over a network / performing repetitive calculations / electronic recordkeeping / storing and retrieving information in memory / electronically scanning or extracting data from a physical document, which the courts have recognized as well‐understood, routine, and conventional when they are claimed in a generic manner. See MPEP § 2106.05(d)(II).).
…using a machine learning model… (Uses a computer as a tool to perform an abstract idea (MPEP 2106.05(f)) Furthermore, the additional element is directed to application of a computer tool (machine learning model), which is not indicative of significantly more (MPEP 2106.05(f)).)
Claims 9 and 19 are rejected on the dame grounds as Claim 1.
Regarding claim 2 it is dependent upon claim 1, and thereby incorporates the limitations of, and corresponding analysis applied to claim 1. Further, claim 2 recites receiving training data including a sample measurement result and a sample partial layout corresponding to the sample measurement result; (In step 2A, prong 2, this recites insignificant extra solution activity of mere data gathering, which is not indicative of integration into a practical application (MPEP 2106.05(g)). In step 2B, this recites receiving data over a network which is a well-understood, routine and conventional activity, which is not indicative of significantly more.) and training the machine learning model to generate the predicted measurement result based on the training data. (In step 2A prong 2, merely training a generic machine learning operation constitutes “applying” the machine learning operation (MPEP 2106.05(f)). In step 2B, merely applying a generic machine learning operation is not indicative of significantly more.)
Claims 10 and 20 are rejected on the dame grounds as Claim 2.
Regarding claim 3 it is dependent upon claim 2, and thereby incorporates the limitations of, and corresponding analysis applied to claim 2. Further, claim 3 recites encoding the sample measurement result and the sample partial layout to obtain a measurement embedding and a layout embedding, respectively, in a same embedding space; (In step 2A, prong 1, this recites both a mental process and a mathematical concept without significantly more. A person can mentally encode sample measurement results and sample partial layouts by a process of simply evaluating the sample measurement results and the sample partial layout and making a judgement on how they should be encoded. Further the Act of encoding is directed towards mathematical a mathematical relationship or a mathematical calculation to determine the embeddings (MPEP 2106). and computing a loss function based on the measurement embedding and a layout embedding. (In step 2A, prong 1, this recites a mathematical process without significantly more. The computing of a loss function is directed to a mathematical calculation (MPEP 2106).)
Claim 11 is rejected on the dame grounds as Claim 3.
Regarding claim 4 it is dependent upon claim 1, and thereby incorporates the limitations of, and corresponding analysis applied to claim 1. Further, claim 3 recites detecting an overlap among the plurality of partial layouts, wherein the representative partial layout is based on the detected overlap. (In step 2A, prong 1, this recites a mental process without significantly more. A person can mentally detect if partial layers overlap by a process of simply evaluating the partial layouts and make a judgement on if they overlap. (MPEP 2106).)
Claim 12 is rejected on the dame grounds as Claim 4.
Regarding claim 5 it is dependent upon claim 1, and thereby incorporates the limitations of, and corresponding analysis applied to claim 1. Further, claim 5 recites performing a layout conversion on the representative partial layout, wherein the layout conversion comprises a size conversion, a rotation conversion, or both. (In step 2A, prong 1, this recites a mental process without significantly more. A person can mentally perform conversions on a representative partial layout by a process of simply evaluating the partial layouts and making a judgement on how the partial layout should be converted (MPEP 2106).)
Claim 13 is rejected on the dame grounds as Claim 5.
Regarding claim 6 it is dependent upon claim 1, and thereby incorporates the limitations of, and corresponding analysis applied to claim 1. Further, claim 6 recites receiving position data including wafer position data indicating a layout position on a wafer, semiconductor position data indicating a layout position on a semiconductor, or both, wherein the predicted measurement result is based on the position data. (In step 2A, prong 2, this recites insignificant extra solution activity of mere data gathering, which is not indicative of integration into a practical application (MPEP 2106.05(g)). In step 2B, this recites receiving data over a network which is a well-understood, routine and conventional activity, which is not indicative of significantly more.)
Claim 14 is rejected on the dame grounds as Claim 6.
Regarding claim 7 it is dependent upon claim 1, and thereby incorporates the limitations of, and corresponding analysis applied to claim 1. Further, claim 7 recites wherein the predicted measurement result comprises a predicted scanning electron microscope (SEM) image. (In step 2A, prong 2, this recites generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))). In step 2B, generally linking the use of the judicial exception to a particular technological environment is not indicative of significantly more.)
Claim 17 is rejected on the dame grounds as Claim 7.
Regarding claim 8 it is dependent upon claim 1, and thereby incorporates the limitations of, and corresponding analysis applied to claim 1. Further, claim 8 recites wherein the predicted measurement result comprises a critical dimension risk index. (In step 2A, prong 2, this recites generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))). In step 2B, generally linking the use of the judicial exception to a particular technological environment is not indicative of significantly more.)
Claim 18 is rejected on the dame grounds as Claim 8.
Regarding claim 15 it is dependent upon claim 9, and thereby incorporates the limitations of, and corresponding analysis applied to claim 9. Further, claim 15 recites wherein the apparatus for inferring semiconductor measurement results comprises an inspection apparatus in a semiconductor process control. (In step 2A, prong 2, this recites generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))). In step 2B, generally linking the use of the judicial exception to a particular technological environment is not indicative of significantly more.)
Regarding claim 16 it is dependent upon claim 9, and thereby incorporates the limitations of, and corresponding analysis applied to claim 9. Further, claim 16 recites wherein the apparatus for inferring semiconductor measurement results comprises a review apparatus in a semiconductor process control. (In step 2A, prong 2, this recites generally linking the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))). In step 2B, generally linking the use of the judicial exception to a particular technological environment is not indicative of significantly more.)
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a) as being anticipated by Hunsche et al. Pub. No.: US 20220327364 A1.
Regarding Claim 1 Hunsche teaches A method comprising: receiving layout data representing a layout of a semiconductor; (Hunsche, paragraph 0032-0034 and 0171, teaches a step of receiving information about geometry information and/or process information for a pattern which is data that represents the layout of a semiconductor.)
generating a plurality of partial layouts based on the layout data; (Hunsche, paragraph 0134 and 0171, teaches the generating of simulated aerial images of the semiconductor substrates (i.e. layout) based on the information provided by the input data.)
selecting a representative partial layout among the plurality of partial layouts; (Hunsche, paragraph 0134 and 0171, teaches the use of aerial image dimensional intensity distributions as inputs, these intensity distributions are a representation based on all of the aerial images that are generated.)
and generating, using a machine learning model, a predicted measurement result for the semiconductor based on the representative partial layout. (Hunsche, paragraph 0134-0135 and 0171, teaches the generating of pattern probability images that represent the measurements that the semiconductors are predicted to have based on the simulated aerial images.)
Claims 9 and 19 are rejected on the dame grounds as Claim 1.
Regarding Claim 2 Hunsche teaches The method of claim 1, further comprising: receiving training data including a sample measurement result and a sample partial layout corresponding to the sample measurement result; and training the machine learning model to generate the predicted measurement result based on the training data. (Hunsche, Paragraph 0170-0172, teaches receiving training samples that comprise both the input and the expected output of the machine learning model. These inputs can be simulated aerial images (i.e. sample partial layouts) and the expected results can be pattern probability images (i.e. sample measurement results). It then teaches the training the model based on these inputs and outputs.)
Claims 10 and 20 are rejected on the dame grounds as Claim 2.
Regarding Claim 3 Hunsche teaches The method of claim 2, wherein the training of the machine learning model comprises: encoding the sample measurement result and the sample partial layout to obtain a measurement embedding and a layout embedding, respectively, in a same embedding space; and computing a loss function based on the measurement embedding and a layout (Hunsche, Paragraph 0165-0170, teaches the encoding of input and outputs into vectors that are both in a vector or feature space. These inputs can be simulated aerial images (i.e. sample partial layouts) and the expected results can be pattern probability images (i.e. sample measurement results). It then teaches the training the model based on these inputs and outputs. Further Hunsche teaches, the use of a cost function (i.e. loss function) that can compare two evaluation points which can be feature vectors of the input and output of the machine learning model.)
Claims 11 are rejected on the dame grounds as Claim 3.
Regarding Claim 4 Hunsche teaches The method of claim 1, further comprising: detecting an overlap among the plurality of partial layouts, wherein the representative partial layout is based on the detected overlap. (Hunsche, paragraph 0134 and 0171, teaches the use of aerial image dimensional intensity distributions as inputs, these intensity distributions are a representation based on all of the aerial images that are generated. The intensity distribution represents overlaps of the simulated aerial images and demonstrates the most intense areas of overlap)
Claim 12 is rejected on the dame grounds as Claim 4.
Regarding Claim 5 Hunsche teaches The method of claim 1, wherein: performing a layout conversion on the representative partial layout, wherein the layout conversion comprises a size conversion, a rotation conversion, or both. (Hunsche, paragraph 0165, teaches the distortion, and/or shifting of the images of the patterns of the semiconductors.)
Claim 13 is rejected on the dame grounds as Claim 5.
Regarding Claim 6 Hunsche teaches The method of claim 1, further comprising: receiving position data including wafer position data indicating a layout position on a wafer, semiconductor position data indicating a layout position on a semiconductor, or both, wherein the predicted measurement result is based on the position data. (Hunsche, paragraph 0058, 0065-0067, and 0088, teaches the receiving of geometry information as an input of the machine learning model, the geometry information comprising the position of features of the pattern on the semiconductor substrate.)
Claim 14 is rejected on the dame grounds as Claim 6.
Regarding Claim 7 Hunsche teaches The method of claim 1, wherein the predicted measurement result comprises a predicted scanning electron microscope (SEM) image. (Hunsche, paragraph 0135, teaches the predicted pattern probability images being traditionally produced from SEM images)
Claim 17 is rejected on the dame grounds as Claim 7.
Regarding Claim 8 Hunsche teaches The method of claim 1, wherein the predicted measurement result comprises a critical dimension risk index. (Hunsche, paragraph 0202-0209, teaches the calculation of an edge placement error (EPE) which utilizes the critical dimensions of the semiconductor and makes a determination on potential defect areas of the semiconductor which are areas of potential risk or weak points.)
Claim 18 is rejected on the dame grounds as Claim 8.
15. The apparatus of claim 9, wherein the apparatus for inferring semiconductor measurement results comprises an inspection apparatus in a semiconductor process control. (Hunsche, paragraph 0244, teaches the use of an inspection apparatus in the semiconductor process control system.)
16. The apparatus of claim 9, wherein the apparatus for inferring semiconductor measurement results comprises a review apparatus in a semiconductor process control. (Hunsche, paragraph 0214, teaches the ability for the manufacturing apparatus to review the potential defects and determine adjustments for the apparatus. (i.e. review apparatus))
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS B LANE whose telephone number is (571)272-1872. The examiner can normally be reached M-Th: 6:40am-4:40pm; F: Out of Office.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARIELA REYES can be reached at (571) 270-1006. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THOMAS BERNARD LANE/ Examiner, Art Unit 2142
/HAIMEI JIANG/ Primary Examiner, Art Unit 2142
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