DETAILED ACTION
This Office Action is in response to Applicant’s application 18/542,995 filed on December 18, 2023 in which claims 1 to 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings submitted on December 18, 2023 have been reviewed and accepted by the Examiner.
Information Disclosure Statement
The Information Disclosure Statement (IDS), filed on December 18, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner.
Notation
References to patents will be in the form of [C:L] where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of [xxxx].
Claim Objections
Claims 1 and 12 are objected to because of the following informalities: The claims recite ‘the stacked nanosheet FETs’ at lines 4 and 5 respectively which lack antecedent basis. Examiner suggests ‘stacked field effect transistor (FET)’ consistent with lines 2 and 3 respectively. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. 2023/0088578 (Thomson) and Horiguchi, Naoto, and Eric Beyne, “Backside Power Delivery.” IMEC, November 25, 2022 Downloaded from URL<www.imec-int.com/en/articles/how-power-chips-backside> on February 25, 2026 (Horiguchi).
Regarding claim 1 Thomson discloses at annotated Figure 4A, a semiconductor device comprising:
PNG
media_image1.png
618
741
media_image1.png
Greyscale
a stacked field effect transistor (FET), as annotated where 108 includes the gate electrode and gate dielectric [0037, 59] formed on a substrate, 101/104 [0070], and connected to a backside metal line, 115 [0047]; and
a lateral junction diode, as annotated and discussed at [0034, 37, 55, 37] co-integrated with the stacked nanosheet FET, as shown.
Thomson does not explicitly teach that the metal line is of a backside power distribution network (BSPDN).
Horiguchi is directed to improvements in transistor performance using back side power distribution networks. Horiguchi teaches inter alia and at Figure 2 that backside power delivery decouples direct power delivery to transistors using wider and less resistive lines, relative to front side power delivery, resulting in improved (lower) IR drop and reduced routing congestion.
PNG
media_image2.png
854
1062
media_image2.png
Greyscale
Taken as a whole the prior art is directed to improvements in FET performance. Horiguchi teaches that when back side metal interconnect is integrated into a power delivery network, that routing congestion decreases and IR drop decreases. An artisan would find it desirable to minimize IR drop (voltage droop) for power delivery to improve performance and to minimize routing congestion to facilitate fewer design rule violations and automated routing software.
Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 1 wherein the metal line is of a backside power distribution network (BSPDN) to improve IR drop for power delivery and decrease routing congestion, as taught by Horiguchi, and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Furthermore, Examiner takes the position that with respect to ‘co-integrated’ even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698 (Fed. Cir. 1985). The structure implied by the process steps should be considered when assessing the patentability of product-by-process claims over the prior art, especially where the product can only be defined by the process steps by which the product is made, or where the manufacturing process steps would be expected to impart distinctive structural characteristics to the final product. In re Garnero, 412 F.2d 276, 279 (CCPA 1979). Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed
PNG
media_image3.png
707
600
media_image3.png
Greyscale
product and the prior art product. In re Marosi, 710 F.2d 798, 802 (Fed. Cir. 1983). See MPEP 2113.
Regarding claim 2 which depends upon claim 1 at Figure 1A, Thomson teaches an alternative embodiment wherein the stacked FET includes a bottom FET, i.e., lower devices, including a bottom nanosheet stack, 101a is described as a nano-ribbon at 00056], in contact with a bottom epitaxial layer, 107b described as a epitaxial layer at [0040], and a top FET, i.e., upper devices, including a top nanosheet stack, 101a described as a nano-ribbon at [0056], in contact with a top epitaxial layer, 107a described as an epitaxial layer at [0040].
Regarding claim 3 which depends upon claim 1, Thomson teaches the stacked FET includes a gate electrode 108 [0035].
Regarding claim 12 and referring to the discussion at claim 1, Thomson discloses an electronic device comprising:
a semiconductor device including a stacked field effect transistor (FET), as annotated and described at [0034], formed on a substrate, 110/104 [0070], and connected to a backside metal line, 115 [0047], and
a lateral junction diode, as annotated and described at [0034, 37, 55], co-integrated with the stacked nanosheet FET as shown.
Thomson does not explicitly teach the metal line is of a backside power distribution network (BSPDN).
Horiguchi is directed to improvements in transistor performance using back side power distribution networks. Horiguchi teaches inter alia that backside power delivery decouples direct power delivery to transistors using wider and less resistive lines, relative to front side power delivery, resulting in improved (lower) IR drop and reduced routing congestion.
Taken as a whole the prior art is directed to improvements in FET performance. Horiguchi teaches that when back side metal interconnect is integrated into a power delivery network, that routing congestion decreases and IR drop decreases. An artisan would find it desirable to minimize IR drop (voltage droop) for power delivery to improve performance and to minimize routing congestion to facilitate fewer design rule violations.
Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 12 wherein the metal line is of a backside power distribution network (BSPDN) to improve IR drop for power delivery and decrease routing congestion, as taught by Horiguchi, and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Furthermore, Examiner takes the position that with respect to ‘co-integrated’ even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698 (Fed. Cir. 1985). The structure implied by the process steps should be considered when assessing the patentability of product-by-process claims over the prior art, especially where the product can only be defined by the process steps by which the product is made, or where the manufacturing process steps would be expected to impart distinctive structural characteristics to the final product. In re Garnero, 412 F.2d 276, 279 (CCPA 1979). Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802 (Fed. Cir. 1983). See MPEP 2113.
Regarding claim 13 which depends upon claim 12 at Figure 1A, Thomson teaches an alternative embodiment wherein the stacked FET includes a bottom FET, i.e., lower devices, including a bottom nanosheet stack, 101a is described as a nano-ribbon at 00056], in contact with a bottom epitaxial layer, 107b described as a epitaxial layer at [0040], and a top FET, i.e., upper devices, including a top nanosheet stack, 101a described as a nano-ribbon at [0056], in contact with a top epitaxial layer, 107a described as an epitaxial layer at [0040].
Regarding claim 14 which depends upon claim 12, Thomson teaches the stacked FET includes a gate electrode,108 [0035].
Allowable Subject Matter
Claims 4-11 and 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4 the prior art fails to teach the device of claim 1, wherein the lateral junction diode includes a P+ region and a N+ region formed at a same first level in the substrate, and the stacked FET is formed at a second level that is different than the first level.
Claims 5-11 depend directly or indirectly on claim 4 and are allowable on that basis.
Regarding claim 15 the prior art fails to teach the device of claim 12, wherein the lateral junction diode includes a P+ region and a N+ region formed at a same first level in the substrate, and the stacked FET is formed at a second level that is different than the first level.
Claims 16-20 depend directly or indirectly on claim 15 and are allowable on that basis.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joe Schoenholtz whose telephone number is (571)270-5475. The examiner can normally be reached M-Thur 7 AM to 7 PM PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ms. Yara Green can be reached at (571) 272-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.E. Schoenholtz/Primary Examiner, Art Unit 2893