DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin US (2015/0287688).
Regarding claim 1, Lin discloses, in FIG. 2 and in related text, an interconnect substrate comprising:
an interconnect layer (201) (see Lin, [0049], [0068]);
an insulating layer (208) covering the interconnect layer (see Lin, [0049]);
an electrode (207, 212) disposed on an upper surface of the interconnect layer (201) and protruding from an upper surface of the insulating layer (208) (see Lin, [0049], [0073]-[0074], [0092]); and
a groove formed in the upper surface of the insulating layer (208) around the electrode (207, 212) (see Lin, FIG. 2: the opening in insulating layer 208 is considered as a groove),
wherein the electrode includes:
a first portion (207) whose side surface is covered with the insulating layer (208);
a second portion (212) whose entire side surface is located outside (away from or above) the insulating layer (208), the second portion being partially located inside the groove (opening in insulating layer 208) and partially protruding above the upper surface of the insulating layer (208) (see Lin, FIG. 2); and
a metal layer (216) covering both an upper surface of the second portion and the entire side surface of the second portion (212) (see Lin, FIG. 2, [0049]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 2009/0020322) in view of Wikipedia (Wikipedia, Solder mask, 20 April 2021) and Koep (US 2014/0328039).
Regarding claim 1, Hsu discloses, in FIG. 4E and in related text, an interconnect substrate comprising:
an interconnect layer (331, 332) (see FIGS. 3I and 4E);
a solder resist layer (36) covering the interconnect layer;
an electrode (34, 35) disposed on an upper surface of the interconnect layer (332) and protruding from an upper surface of the solder resist layer (36); and
a groove formed in the upper surface of the solder resist layer (36) around the electrode (35),
wherein the electrode includes:
a first portion (34) whose side surface is covered with the solder resist layer (36);
a second portion (35) whose entire side surface is located outside (away from) the solder resist layer (36), the second portion being partially located inside the groove and partially protruding above the upper surface of the solder resist layer; and
a solder material layer (37’) covering both an upper surface of the second portion and the entire side surface of the second portion (35) (see Hsu, [0036]-[0042], [0053], [0057]).
Hsu does not explicitly disclose the solder resist layer is an insulating layer. Hsu does not explicitly disclose an insulating layer.
Wikipedia teaches a solder resist layer is an insulating polymer layer (see Wikipedia, first paragraph). Thus Wikipedia teaches an insulating layer.
Hsu and Wikipedia are analogous art because they both are directed to device packaging and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsu with the features of Wikipedia because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Hsu to include an insulating layer, as taught by Wikipedia, to prevent unintended electrical connection and oxidation (see Wikipedia, first paragraph).
Hsu does not explicitly disclose the solder material layer being a metal layer. Hsu does not explicitly disclose a metal layer.
Koep teaches solder material containing nickel (see Koep, [0029]). Thus Koep teaches a metal layer (a nickel layer).
Hsu and Koep are analogous art because they both are directed to device packaging and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsu with the features of Koep because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Hsu to include a metal layer, as taught by Koep, because it is simple substitution of one known element for another (nickel as solder material) to obtain predictable results (for solder bump connection). See MPEP § 2143.
Regarding claim 3, Hsu in view of Wikipedia and Koep teaches the interconnect structure of claim 1.
Koep teaches wherein the metal layer includes a nickel layer, a nickel alloy layer, a cobalt layer, or a cobalt alloy layer (see discussion on claim 1 above), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 1.
Regarding claim 4, Hsu in view of Wikipedia and Koep teaches the interconnect structure of claim 1.
Hsu discloses wherein the electrode and the solder material layer constitute an external connection terminal for electrical connection to a semiconductor chip (see Hsu, [0057]).
Koep teaches the metal layer (see discussion on claim 1 above), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 1.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Wikipedia and Koep, and further in view of Rokugawa (US 2016/0005685).
Regarding claim 5, Hsu in view of Wikipedia and Koep teaches the interconnect structure of claim 4.
Hsu discloses wherein the external connection terminal and the semiconductor chip are electrically connected to each other through solder (see Hsu, [0057]).
Hsu does not explicitly disclose a connection terminal of the semiconductor chip; the semiconductor chip mounted on the interconnect substrate.
Rokugawa teaches a connection terminal (60b) of the semiconductor chip (60); the semiconductor chip mounted on the interconnect substrate (10) (see Rokugawa, FIGS. 1A-1B, [0036]).
Hsu and Rokugawa are analogous art because they both are directed to device packaging and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsu with the features of Rokugawa because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Hsu to include a connection terminal of the semiconductor chip; the semiconductor chip mounted on the interconnect substrate, as taught by Rokugawa, to provide integration of semiconductor elements (see Rokugawa, [0004]).
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of records, individually or in combination, do not disclose nor teach “wherein the metal layer fills the groove” in combination with other limitations as recited in claim 2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time.
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/SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811