DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the
“the gate electrode at least partially surrounds the channel region in a plan view." of Claim 6
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 6, 7, 9 and 10 is/are rejected under 35 U.S.C. 102(A1) as being anticipated by Shivaraman et al. (US 2021/0111179 A1).
Regarding Claim 1, Shivaraman (Fig. 2) discloses a semiconductor memory device comprising:
a substrate (226);
a channel region (212) on the substrate (226);
first and second source/drain regions (208 on both side of the channel) electrically connected to the channel region (212);
a gate electrode (210) that extends in a first direction and is on the channel region (212);
a conductive line (220) that extends in a second direction intersecting the first direction and is electrically connected to the second source/drain region (208 under 220) (“node 220 extends down to a top of a substrate 226 and connects to the source of the access transistor 206”) [0044]; and
a capacitor structure (202) electrically connected to the first source/drain region (208) on the substrate, wherein the capacitor structure comprises:
a plurality of first electrodes (216) stacked and spaced apart from each other in a third direction perpendicular to an upper surface of the substrate (226);
a plurality of trenches (222) that extend into the plurality of first electrodes (216);
a capacitor dielectric film (224) that extends along side walls of each of the plurality of trenches (222); and
a plurality of second electrodes (220, Node) in the plurality of trenches (222), respectively.
Regarding Claim 3, Shivaraman discloses the semiconductor memory device of claim 1, wherein the capacitor dielectric film (224) comprises zirconium oxide, hafnium-zirconium oxide, lead-zirconium oxide or sodium-niobium oxide. [0032]
Regarding Claim 6, Shivaraman discloses the semiconductor memory device of claim 1, wherein
the channel region (212) protrudes from the substrate (226) in the third direction, and wherein
the gate electrode (210) at least partially surrounds the channel region (212) in a plan view. (fin field effect transistor (FinFET) for instance.) (Fig. 2)
Regarding Claim 7, Shivaraman discloses the semiconductor memory device of claim 1, wherein
the first source/drain region (208 on side of the channel) is electrically connected to one of the plurality of second electrodes (220, Node).
Regarding Claim 9, Shivaraman discloses the semiconductor memory device of claim 1, wherein each of the plurality of trenches has a circular, elliptical or rectangular shape in a plan view. (Fig. 1B,C)
Regarding Claim 10, Shivaraman discloses the semiconductor memory device of claim 1, wherein the plurality of first electrodes (216) each extend in the first direction. (Fig. 1, 2)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shivaraman et al. (US 2021/0111179 A1) in view of Manipatruni et al. (US 2020/0273867 A1).
Regarding Claim 2, Shivaraman (Fig. 2) discloses the semiconductor memory device of claim 1, wherein
the capacitor dielectric film (224) comprises a material. [0032].
Shivaraman does not explicitly disclose a perovskite material or a fluorite material.
Manipatruni discloses a capacitor dielectric film comprises a perovskite material or a fluorite material. [0017-0019]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify he semiconductor memory device in Shivaraman in view of Manipatruni such that a capacitor dielectric film comprises a perovskite material or a fluorite material in order to allow allows for very low voltage switching of the FE state in the FE capacitor since the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (See MPEP 2144.07).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shivaraman et al. (US 2021/0111179 A1) in view of Pan et al. (US 2020/0051607 A1).
Regarding Claim 4, Shivaraman discloses the semiconductor memory device of claim 1.
Shivaraman does not explicitly disclose the channel region comprises polysilicon or indium gallium zinc oxide (IGZO).
Pan discloses a channel region (128) comprises polysilicon or indium gallium zinc oxide (IGZO). [0085, 0090].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify he semiconductor memory device in Shivaraman in view of Pan such that the channel region comprises polysilicon or indium gallium zinc oxide (IGZO) in order to make transistor for 3D ferroelectric memory device and since the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (See MPEP 2144.07).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shivaraman et al. (US 2021/0111179 A1) in view of Oh et al. (US 2021/0391350 A1).
Regarding Claim 5, Shivaraman discloses the semiconductor memory device of claim 1, wherein
the gate electrode (210).
Shivaraman does not explicitly disclose the gate electrode is in the substrate.
Oh (Fig. 13D) discloses a gate electrode (550) is in a substrate. (501)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify he semiconductor memory device in Shivaraman in view of Oh such that the gate electrode is in the substrate in order to have buried channel array transistor (BCAT) and overcome a short channel effect of a DRAM structure by including a gate electrode embedded in a trench. [0163-0164]
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shivaraman et al. (US 2021/0111179 A1) in view of Sel et al. (US 2019/0034125 A1).
Regarding Claim 8, Shivaraman discloses the semiconductor memory device of claim 1, wherein
each of the plurality of first electrodes (216) comprises is in contact with the capacitor dielectric film (224).
Shivaraman does not explicitly disclose that each of the plurality of first electrodes comprises a first sub-film that is spaced apart from the capacitor dielectric film.
Sel (Fig. 2B, 3A) discloses each of a plurality of first electrodes (322, 324, 328) comprises a first sub-film (322) that is spaced apart from a capacitor dielectric film (214), and a second sub-film (324, 328) that is in contact with the capacitor dielectric film (214).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify he semiconductor memory device in Shivaraman in view of Sel such that each of the plurality of first electrodes comprises a first sub-film that is spaced apart from the capacitor dielectric film in order to have BMC memory cell includes a barrier modulated switching structure. [0083]
Claim(s) 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shivaraman et al. (US 2021/0111179 A1) in view of Haratipour et al. (US 2022/0208778 A1)
Regarding Claim 11, Shivaraman (Fig. 1) discloses a semiconductor memory device comprising:
a substrate (118) are patterned in the semiconductor substrate or layer.) including a first region (region around transistors)
a plurality of transistors (transistors in Fig. 2) that are on the first region of the substrate (226), wherein
ones of the plurality of transistors each include a gate electrode (210, WL1, WL2), a channel region (212), and a source/drain region (208); and
a capacitor structure (capacitor) electrically connected to the source/drain region (208) of each of the ones of the plurality of transistors (transistors in Fig. 2), wherein
the capacitor structure comprises:
a plurality of first electrodes (216) that extend in a first direction, are stacked and spaced apart from each other in a third direction perpendicular to an upper surface of the substrate (226),
a plurality of second electrodes (222) that extend in a second direction intersecting the first direction on the first region of the substrate (226), extend into the plurality of first electrodes (216), and are electrically connected to the source/drain region (208) of each of the ones of the plurality of transistors (transistors in Fig. 2), respectively; and
a capacitor dielectric film (224) between respective ones of the plurality of first electrodes (216) and respective ones of the plurality of second electrodes (222).
Shivaraman does not explicitly disclose a substrate including a second region and a plurality of first electrodes have a stepped profile on the second region of the substrate.
Haratipour (Fig. 1) discloses a substrate (“the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer”) including a second region (substrate around below 126) and a plurality of first electrodes (102) have a stepped profile on the second region of the substrate (See Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify he semiconductor memory device in Shivaraman in view of Haratipour such that a substrate including a second region and a plurality of first electrodes have a stepped profile on the second region of the substrate in order to have each via to land on respective first electrodes and to have 3D array of two or more stacks of ferroelectric capacitors [0027]
Regarding Claim 12, Shivaraman in view of Haratipour discloses the semiconductor memory device of claim 11, wherein
the gate electrode extends in the first direction. (Fig. 2 Shivaraman)
Regarding Claim 13, Shivaraman in view of Haratipour discloses the semiconductor memory device of claim 11, wherein
at least one of the plurality of transistors comprises a buried transistor (BCAT), a planar transistor, a fin-shaped transistor (FinFET) or a vertical channel transistor (VCT). (“access transistor 206 comprises a horizontally-oriented non-planar transistor, such as fin field effect transistor (FinFET) for instance.) [0036]
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shivaraman et al. (US 2021/0111179 A1) in view of Haratipour et al. (US 2022/0208778 A1) and further in view of Pan et al. (US 2020/0051607 A1).
Regarding Claim 14, Shivaraman in view of Haratipour discloses the semiconductor memory device of claim 11.
Shivaraman in view of Haratipou does not explicitly disclose the channel region comprises polysilicon or indium gallium zinc oxide (IGZO)
Pan discloses a channel region (128) comprises polysilicon or indium gallium zinc oxide (IGZO). [0085, 0090].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify he semiconductor memory device in Shivaraman in view of Haratipour and Pan such that the channel region comprises polysilicon or indium gallium zinc oxide (IGZO) in order to make transistor for 3D ferroelectric memory device and since the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (See MPEP 2144.07).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shivaraman et al. (US 2021/0111179 A1) in view of Manipatruni et al. (US 2020/0273867 A1).
Regarding Claim 15, Shivaraman in view of Haratipour discloses the semiconductor memory device of claim 11, wherein
the capacitor dielectric film comprises a material. [0042]
Shivaraman in view of Haratipour does not explicitly disclose a perovskite material or a fluorite material.
Manipatruni discloses a capacitor dielectric film comprises a perovskite material or a fluorite material. [0017-0019]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify he semiconductor memory device in Shivaraman in view of Haratipour and Manipatruni such that a capacitor dielectric film comprises a perovskite material or a fluorite material in order to allow allows for very low voltage switching of the FE state in the FE capacitor since the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (See MPEP 2144.07).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shivaraman et al. (US 2021/0111179 A1) in view of Haratipour et al. (US 2022/0208778 A1) and further in view of Kim et al. (US 2015/0318296 A1).
Regarding Claim 16, Shivaraman in view of Haratipour discloses the semiconductor memory device of claim 11,
wherein each of the plurality of second electrodes (222, 120, node) has a shape in a plan view (Fig. 1B).
Shivaraman in view of Haratipour does not explicitly disclose wherein each of the plurality of second electrodes has an elliptical shape in a plan view, wherein the elliptical shape extends longitudinally in a second direction.
Kim (Fig. 11) discloses each of the plurality of second electrodes (236-1) has an elliptical shape in a plan view (Fig. 11), wherein the elliptical shape extends longitudinally in a second direction (Fig. 11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify he semiconductor memory device in Shivaraman in view of Haratipour and Kim such that a capacitor dielectric film comprises a perovskite material or a fluorite material in order to increase capacitance of the plurality of vertical capacitors [0095-0097] and since a change in shape of an element was considered a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration was significant (In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (MPEP §2144.04)
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shivaraman et al. (US 2021/0111179 A1) in view of Haratipour et al. (US 2022/0208778 A1) and further in view of Karda et al. (US 2018/0323214 A1).
Regarding Claim 17, Shivaraman in view of Haratipour discloses the semiconductor memory device of claim 11.
Shivaraman in view of Haratipour does not explicitly disclose an electrode cutting structure that extends in the first direction, wherein the electrode cutting structure extends into the plurality of first electrodes between respective ones of the plurality of second electrodes.
Karda (Fig. 10) discloses an electrode cutting structure (33) that extends in the first direction, wherein the electrode cutting structure (333) extends into a plurality of first electrodes (46) between respective ones of a plurality of second electrodes (16). [0041]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify he semiconductor memory device in Shivaraman in view of Haratipour and Kards such that a capacitor dielectric film comprises a perovskite material or a fluorite material in order to electrically isolate a plurality of second electrodes relative one another [0041]
Claim(s) 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shivaraman et al. (US 2021/0111179 A1) in view of Ramaswamy (US 2020/0381290 A1).
Regarding Claim 18, Shivaraman (Fig. 2) discloses the semiconductor memory device comprising:
cell structure that includes a plurality of memory cells (“3D FRAM memory array 250”) [0042]
wherein
each of the plurality of memory cells (200) includes a transistor (206) and at least two capacitors (See 202 on PL1-PL4) electrically connected to the transistor (206), wherein
each of the at least two capacitors (See 202 on PL1-PL4) comprises:
a first electrode (216) extending in a second direction (horizontal) that intersects the first direction;
a second electrode (222) that extends into the first electrode (216) and is electrically connected to a source/drain region (“node 220 extends down to a top of a substrate 226 and connects to the source of the access transistor 206”) [0044] of the transistor (206); and
a capacitor dielectric film (224) including a ferroelectric material (“a ferroelectric/antiferroelectric material 224”) between the first electrode (216) and the second electrode (222, node).
Shivaraman does not explicitly disclose a peripheral circuit structure including a peripheral circuit element; a cell structure that includes a plurality of memory cells and overlaps the peripheral circuit structure in a first direction, the peripheral circuit element is configured to control an operation of at least one of the plurality of memory cells.
Ramaswamy (Fig. 1) discloses a peripheral circuit structure (82) including a peripheral circuit element (84); a cell structure (80) that includes a plurality of memory cells (80) and overlaps the peripheral circuit structure (82) in a first direction (Fig. 1), the peripheral circuit element (84) is configured to control an operation of at least one of the plurality of memory cells (80) . (“the base 82 comprises the peripheral region 14 having circuitry 84 utilized for driving the wordlines (e.g., WL-1, WL-2, WL-3, WL-4 and WL-5), and circuitry 86 utilized for driving the bitlines (e.g., BL-1).” ) [0057].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify he semiconductor memory device in Shivaraman in view of Ramaswamy such that a peripheral circuit structure including a peripheral circuit element; a cell structure that includes a plurality of memory cells and overlaps the peripheral circuit structure in a first direction, the peripheral circuit element is configured to control an operation of at least one of the plurality of memory cells in order to peripheral region having circuitry utilized for driving memory cells [0057].
Regarding Claim 19, Shivaraman in view of Ramaswamy discloses the semiconductor memory device of claim 18, wherein
the transistor comprises a buried transistor (BCAT), a planar transistor, a fin-shaped transistor (FinFET) or a vertical channel transistor (VCT). (“access transistor 206 comprises a horizontally-oriented non-planar transistor, such as fin field effect transistor (FinFET) for instance.”) [0036]
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shivaraman et al. (US 2021/0111179 A1) in view of Ramaswamy (US 2020/0381290 A1) and further in view of Pan et al. (US 2020/0051607 A1).
Regarding Claim 20, Shivaraman in view of Ramaswamy discloses the semiconductor memory device of claim 18.
Shivaraman in view of Ramaswamy does not explicitly disclose a channel region of the transistor comprises polysilicon or indium gallium zinc oxide (IGZO).
Pan discloses a channel region (128) comprises polysilicon or indium gallium zinc oxide (IGZO). [0085, 0090].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify he semiconductor memory device in Shivaraman in view of Ramaswamy and Pan such that the channel region comprises polysilicon or indium gallium zinc oxide (IGZO) in order to make transistor for 3D ferroelectric memory device and since the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (See MPEP 2144.07).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached on M-F 9a.m.-6p.m.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached on (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DMITRIY YEMELYANOV/Examiner, Art Unit 2891
Prosecution Insights