Prosecution Insights
Last updated: October 01, 2026
Application No. 18/543,338

MAKING A QUANTUM DEVICE WITH AN EMBEDDING JOSEPHSON JUNCTION

Non-Final OA §102§112
Filed
Dec 18, 2023
Priority
Dec 20, 2022 — FR 2213899 +1 more
Examiner
PATERSON, BRIGITTE A
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Commissariat à l'Énergie Atomique et aux Énergies Alternatives
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
297 granted / 388 resolved
+8.5% vs TC avg
Strong +23% interview lift
Without
With
+22.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
21 currently pending
Career history
411
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
46.6%
+6.6% vs TC avg
§102
27.0%
-13.0% vs TC avg
§112
23.6%
-16.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 388 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 3, 8, 10-13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08/28/2026. Claim Objections Claim 2 is objected to because of the following informalities: claim 2 recites “wherein the trap rich layer is of hydrogenated amorphous silicon (aSi:H) or polysilicon”. Appropriate correction is required. Suggestion: “wherein the trap rich layer is made of hydrogenated amorphous silicon (aSi:H) or polysilicon” Claim 4 is objected to because of the following informalities: claim 4 recites “wherein the surface layer of the substrate is of a crystalline semiconductor material with a low resistivity of between 10 Ω.cm and 20 Ω.cm.”. Appropriate correction is required. Suggestion: “wherein the surface layer of the substrate is made of a crystalline semiconductor material with a low resistivity of between 10 Ω.cm and 20 Ω.cm.” Claim 6 is objected to because of the following informalities: claim 6 recites “wherein the first metal portion and the second metal portion are of a given superconducting material, in particular aluminium, and wherein the first metal portion is arranged on and in contact with a first metal track, the second metal portion being arranged on and in contact with a second metal track, the first metal track and the second metal track being of a superconducting material different from said given superconducting material”. Appropriate correction is required. Suggestion: “wherein the first metal portion and the second metal portion are made of a given superconducting material, in particular aluminium, and wherein the first metal portion is arranged on and in contact with a first metal track, the second metal portion being arranged on and in contact with a second metal track, the first metal track and the second metal track being made of a superconducting material different from said given superconducting material.” Claim 9 is objected to because of the following informalities: claim 9 recites “wherein a resonator is coupled to the first metal track or to the second metal track, the resonator, the first metal track and the second metal track being disposed facing said protective layer (116).” Appropriate correction is required. Suggestion: change the dependency of claim 9 to claim 6 and remove element number from claim. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-2, 4-7 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites: “the first metal portion and the second metal portion being disposed on and in contact with a so-called "protective" layer1 arranged on the substrate or belonging to the substrate2, said protective layer being a trap rich layer3.” 1 It is unclear what is required of the claim limitation. The use of the term “so-called “protective” layer” renders the claim indefinite because it is unclear what is required of said layer. Does the layer need to provide protection or is it merely “called” a protective layer and there are no physical limits placed on the layer? 2 It is unclear what is required of the claim limitation for the “so-called “protective” layer to belong to the substrate. Does this mean that the so-called “protective” layer is either arranged on the substrate or is formed by modifying the substrate such that some portion “belongs” to the substrate? 3 It is unclear what is required of the claim limitation for the protective layer to be considered “trap rich”. There is no discussion in the originally filed disclosure to determine the minimum amount of charge traps within the protective layer in order to be considered “trap rich”. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-2, 5 and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2011/0089405 A1 (Ladizinsky). Re claim 1, Ladizinsky teaches a Josephson junction quantum device structure comprising: - a substrate (substrate 610) provided with a surface layer of a crystalline semiconductor material, in particular crystalline silicon ([0089]), - at least one Josephson junction (Josephson junctions 670), formed by at least one first metal portion (metal layer 640), of a superconducting material ([0092]), coated with an insulating zone (insulating layer 650), said insulating zone itself being coated with a second metal portion (metal layer 660) of a superconducting material ([0092]) and the second metal portion covering said insulating zone and said first metal portion, the first metal portion and the second metal portion being disposed on and in contact with a so-called "protective" layer (dielectric layer 630 can be hydrogenated amorphous silicon [0089] having 620 embedded therein) arranged on the substrate or belonging to the substrate, said protective layer being a trap rich layer (Fig. 6c [0089-0092]). PNG media_image1.png 465 731 media_image1.png Greyscale Re claim 2, Ladizinsky teaches wherein the trap rich layer is of hydrogenated amorphous silicon (aSi:H) or polysilicon ([0089]). Re claim 5, Ladizinsky teaches wherein the protective layer entirely extends in contact with the surface layer of the substrate (Fig. 6c). Re claim 7, Ladizinsky teaches the trap rich layer being disposed on said surface layer, the trap rich layer being of an amorphous semiconductor material ([0089]) or polycrystalline material or a layer of dielectric material such as silicon nitride. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. BRIGITTE A. PATERSON Primary Examiner Art Unit 2896 /BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Dec 18, 2023
Application Filed
Sep 14, 2026
Non-Final Rejection mailed — §102, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
99%
With Interview (+22.6%)
2y 8m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 388 resolved cases by this examiner. Grant probability derived from career allowance rate.

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